1*4882a593SmuzhiyunQualcomm APQ8064 TLMM block 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: "qcom,apq8064-pinctrl" 5*4882a593Smuzhiyun- reg: Should be the base address and length of the TLMM block. 6*4882a593Smuzhiyun- interrupts: Should be the parent IRQ of the TLMM block. 7*4882a593Smuzhiyun- interrupt-controller: Marks the device node as an interrupt controller. 8*4882a593Smuzhiyun- #interrupt-cells: Should be two. 9*4882a593Smuzhiyun- gpio-controller: Marks the device node as a GPIO controller. 10*4882a593Smuzhiyun- #gpio-cells : Should be two. 11*4882a593Smuzhiyun The first cell is the gpio pin number and the 12*4882a593Smuzhiyun second cell is used for optional parameters. 13*4882a593Smuzhiyun- gpio-ranges: see ../gpio/gpio.txt 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunOptional properties: 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun- gpio-reserved-ranges: see ../gpio/gpio.txt 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunPlease refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for 20*4882a593Smuzhiyuna general description of GPIO and interrupt bindings. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunPlease refer to pinctrl-bindings.txt in this directory for details of the 23*4882a593Smuzhiyuncommon pinctrl bindings used by client devices, including the meaning of the 24*4882a593Smuzhiyunphrase "pin configuration node". 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunQualcomm's pin configuration nodes act as a container for an arbitrary number of 27*4882a593Smuzhiyunsubnodes. Each of these subnodes represents some desired configuration for a 28*4882a593Smuzhiyunpin, a group, or a list of pins or groups. This configuration can include the 29*4882a593Smuzhiyunmux function to select on those pin(s)/group(s), and various pin configuration 30*4882a593Smuzhiyunparameters, such as pull-up, drive strength, etc. 31*4882a593Smuzhiyun 32*4882a593SmuzhiyunThe name of each subnode is not important; all subnodes should be enumerated 33*4882a593Smuzhiyunand processed purely based on their content. 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunEach subnode only affects those parameters that are explicitly listed. In 36*4882a593Smuzhiyunother words, a subnode that lists a mux function but no pin configuration 37*4882a593Smuzhiyunparameters implies no information about any pin configuration parameters. 38*4882a593SmuzhiyunSimilarly, a pin subnode that describes a pullup parameter implies no 39*4882a593Smuzhiyuninformation about e.g. the mux function. 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunThe following generic properties as defined in pinctrl-bindings.txt are valid 43*4882a593Smuzhiyunto specify in a pin configuration subnode: 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun pins, function, bias-disable, bias-pull-down, bias-pull-up, drive-strength, 46*4882a593Smuzhiyun output-low, output-high. 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunNon-empty subnodes must specify the 'pins' property. 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunValid values for pins are: 51*4882a593Smuzhiyun gpio0-gpio89 52*4882a593Smuzhiyun 53*4882a593SmuzhiyunValid values for function are: 54*4882a593Smuzhiyun cam_mclk, codec_mic_i2s, codec_spkr_i2s, gp_clk_0a, gp_clk_0b, gp_clk_1a, 55*4882a593Smuzhiyun gp_clk_1b, gp_clk_2a, gp_clk_2b, gpio, gsbi1, gsbi2, gsbi3, gsbi4, 56*4882a593Smuzhiyun gsbi4_cam_i2c, gsbi5, gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, 57*4882a593Smuzhiyun gsbi6_spi_cs1, gsbi6_spi_cs2, gsbi6_spi_cs3, gsbi7, gsbi7_spi_cs1, 58*4882a593Smuzhiyun gsbi7_spi_cs2, gsbi7_spi_cs3, gsbi_cam_i2c, hdmi, mi2s, riva_bt, riva_fm, 59*4882a593Smuzhiyun riva_wlan, sdc2, sdc4, slimbus, spkr_i2s, tsif1, tsif2, usb2_hsic, ps_hold 60*4882a593Smuzhiyun 61*4882a593SmuzhiyunExample: 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun msmgpio: pinctrl@800000 { 64*4882a593Smuzhiyun compatible = "qcom,apq8064-pinctrl"; 65*4882a593Smuzhiyun reg = <0x800000 0x4000>; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun gpio-controller; 68*4882a593Smuzhiyun #gpio-cells = <2>; 69*4882a593Smuzhiyun interrupt-controller; 70*4882a593Smuzhiyun #interrupt-cells = <2>; 71*4882a593Smuzhiyun interrupts = <0 16 0x4>; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun pinctrl-names = "default"; 74*4882a593Smuzhiyun pinctrl-0 = <&gsbi5_uart_default>; 75*4882a593Smuzhiyun gpio-ranges = <&msmgpio 0 0 90>; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun gsbi5_uart_default: gsbi5_uart_default { 78*4882a593Smuzhiyun mux { 79*4882a593Smuzhiyun pins = "gpio51", "gpio52"; 80*4882a593Smuzhiyun function = "gsbi5"; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun tx { 84*4882a593Smuzhiyun pins = "gpio51"; 85*4882a593Smuzhiyun drive-strength = <4>; 86*4882a593Smuzhiyun bias-disable; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun rx { 90*4882a593Smuzhiyun pins = "gpio52"; 91*4882a593Smuzhiyun drive-strength = <2>; 92*4882a593Smuzhiyun bias-pull-up; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun }; 96