xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/pinmux-node.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Generic pin multiplexing node schema
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Linus Walleij <linus.walleij@linaro.org>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyundescription: |
13*4882a593Smuzhiyun  The contents of the pin configuration child nodes are defined by the binding
14*4882a593Smuzhiyun  for the individual pin controller device. The pin configuration nodes need not
15*4882a593Smuzhiyun  be direct children of the pin controller device; they may be grandchildren,
16*4882a593Smuzhiyun  for example. Whether this is legal, and whether there is any interaction
17*4882a593Smuzhiyun  between the child and intermediate parent nodes, is again defined entirely by
18*4882a593Smuzhiyun  the binding for the individual pin controller device.
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun  While not required to be used, there are 3 generic forms of pin muxing nodes
21*4882a593Smuzhiyun  which pin controller devices can use.
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun  pin multiplexing nodes:
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun  Example:
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun  state_0_node_a {
28*4882a593Smuzhiyun    uart0 {
29*4882a593Smuzhiyun      function = "uart0";
30*4882a593Smuzhiyun      groups = "u0rxtx", "u0rtscts";
31*4882a593Smuzhiyun    };
32*4882a593Smuzhiyun  };
33*4882a593Smuzhiyun  state_1_node_a {
34*4882a593Smuzhiyun    spi0 {
35*4882a593Smuzhiyun      function = "spi0";
36*4882a593Smuzhiyun      groups = "spi0pins";
37*4882a593Smuzhiyun    };
38*4882a593Smuzhiyun  };
39*4882a593Smuzhiyun  state_2_node_a {
40*4882a593Smuzhiyun    function = "i2c0";
41*4882a593Smuzhiyun    pins = "mfio29", "mfio30";
42*4882a593Smuzhiyun  };
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun  Optionally an alternative binding can be used if more suitable depending on the
45*4882a593Smuzhiyun  pin controller hardware. For hardware where there is a large number of identical
46*4882a593Smuzhiyun  pin controller instances, naming each pin and function can easily become
47*4882a593Smuzhiyun  unmaintainable. This is especially the case if the same controller is used for
48*4882a593Smuzhiyun  different pins and functions depending on the SoC revision and packaging.
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun  For cases like this, the pin controller driver may use pinctrl-pin-array helper
51*4882a593Smuzhiyun  binding with a hardware based index and a number of pin configuration values:
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun  pincontroller {
54*4882a593Smuzhiyun    ... /* Standard DT properties for the device itself elided */
55*4882a593Smuzhiyun    #pinctrl-cells = <2>;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun    state_0_node_a {
58*4882a593Smuzhiyun      pinctrl-pin-array = <
59*4882a593Smuzhiyun        0 A_DELAY_PS(0) G_DELAY_PS(120)
60*4882a593Smuzhiyun        4 A_DELAY_PS(0) G_DELAY_PS(360)
61*4882a593Smuzhiyun        ...
62*4882a593Smuzhiyun        >;
63*4882a593Smuzhiyun    };
64*4882a593Smuzhiyun    ...
65*4882a593Smuzhiyun  };
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun  Above #pinctrl-cells specifies the number of value cells in addition to the
68*4882a593Smuzhiyun  index of the registers. This is similar to the interrupts-extended binding with
69*4882a593Smuzhiyun  one exception. There is no need to specify the phandle for each entry as that
70*4882a593Smuzhiyun  is already known as the defined pins are always children of the pin controller
71*4882a593Smuzhiyun  node. Further having the phandle pointing to another pin controller would not
72*4882a593Smuzhiyun  currently work as the pinctrl framework uses named modes to group pins for each
73*4882a593Smuzhiyun  pin control device.
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun  The index for pinctrl-pin-array must relate to the hardware for the pinctrl
76*4882a593Smuzhiyun  registers, and must not be a virtual index of pin instances. The reason for
77*4882a593Smuzhiyun  this is to avoid mapping of the index in the dts files and the pin controller
78*4882a593Smuzhiyun  driver as it can change.
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun  For hardware where pin multiplexing configurations have to be specified for
81*4882a593Smuzhiyun  each single pin the number of required sub-nodes containing "pin" and
82*4882a593Smuzhiyun  "function" properties can quickly escalate and become hard to write and
83*4882a593Smuzhiyun  maintain.
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun  For cases like this, the pin controller driver may use the pinmux helper
86*4882a593Smuzhiyun  property, where the pin identifier is provided with mux configuration settings
87*4882a593Smuzhiyun  in a pinmux group. A pinmux group consists of the pin identifier and mux
88*4882a593Smuzhiyun  settings represented as a single integer or an array of integers.
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun  The pinmux property accepts an array of pinmux groups, each of them describing
91*4882a593Smuzhiyun  a single pin multiplexing configuration.
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun  pincontroller {
94*4882a593Smuzhiyun    state_0_node_a {
95*4882a593Smuzhiyun      pinmux = <PINMUX_GROUP>, <PINMUX_GROUP>, ...;
96*4882a593Smuzhiyun    };
97*4882a593Smuzhiyun  };
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun  Each individual pin controller driver bindings documentation shall specify
100*4882a593Smuzhiyun  how pin IDs and pin multiplexing configuration are defined and assembled
101*4882a593Smuzhiyun  together in a pinmux group.
102*4882a593Smuzhiyun
103*4882a593Smuzhiyunproperties:
104*4882a593Smuzhiyun  function:
105*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/string
106*4882a593Smuzhiyun    description: The mux function to select
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun  pins:
109*4882a593Smuzhiyun    oneOf:
110*4882a593Smuzhiyun      - $ref: /schemas/types.yaml#/definitions/uint32-array
111*4882a593Smuzhiyun      - $ref: /schemas/types.yaml#/definitions/string-array
112*4882a593Smuzhiyun    description:
113*4882a593Smuzhiyun      The list of pin identifiers that properties in the node apply to. The
114*4882a593Smuzhiyun      specific binding for the hardware defines whether the entries are integers
115*4882a593Smuzhiyun      or strings, and their meaning.
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun  groups:
118*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/string-array
119*4882a593Smuzhiyun    description:
120*4882a593Smuzhiyun      the group to apply the properties to, if the driver supports
121*4882a593Smuzhiyun      configuration of whole groups rather than individual pins (either
122*4882a593Smuzhiyun      this, "pins" or "pinmux" has to be specified)
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun  pinmux:
125*4882a593Smuzhiyun    description:
126*4882a593Smuzhiyun      The list of numeric pin ids and their mux settings that properties in the
127*4882a593Smuzhiyun      node apply to (either this, "pins" or "groups" have to be specified)
128*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/uint32-array
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun  pinctrl-pin-array:
131*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/uint32-array
132*4882a593Smuzhiyun
133*4882a593SmuzhiyunadditionalProperties: true
134