1*4882a593Smuzhiyun* ZTE ZX Pin Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe pin controller on ZTE ZX platforms is kinda of hybrid. It consists of 4*4882a593Smuzhiyuna main controller and an auxiliary one. For example, on ZX296718 SoC, the 5*4882a593Smuzhiyunmain controller is TOP_PMM and the auxiliary one is AON_IOCFG. Both 6*4882a593Smuzhiyuncontrollers work together to control pin multiplexing and configuration in 7*4882a593Smuzhiyunthe way illustrated as below. 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun GMII_RXD3 ---+ 11*4882a593Smuzhiyun | 12*4882a593Smuzhiyun DVI1_HS ---+----------------------------- GMII_RXD3 (TOP pin) 13*4882a593Smuzhiyun | 14*4882a593Smuzhiyun BGPIO16 ---+ ^ 15*4882a593Smuzhiyun | pinconf 16*4882a593Smuzhiyun ^ | 17*4882a593Smuzhiyun | pinmux | 18*4882a593Smuzhiyun | | 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun TOP_PMM (main) AON_IOCFG (aux) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun | | | 23*4882a593Smuzhiyun | pinmux | | 24*4882a593Smuzhiyun | pinmux v | 25*4882a593Smuzhiyun v | pinconf 26*4882a593Smuzhiyun KEY_ROW2 ---+ v 27*4882a593Smuzhiyun PORT1_LCD_TE ---+ | 28*4882a593Smuzhiyun | AGPIO10 ---+------ KEY_ROW2 (AON pin) 29*4882a593Smuzhiyun I2S0_DOUT3 ---+ | 30*4882a593Smuzhiyun |-----------------------+ 31*4882a593Smuzhiyun PWM_OUT3 ---+ 32*4882a593Smuzhiyun | 33*4882a593Smuzhiyun VGA_VS1 ---+ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunFor most of pins like GMII_RXD3 in the figure, the pinmux function is 37*4882a593Smuzhiyuncontrolled by TOP_PMM block only, and this type of pins are meant by term 38*4882a593Smuzhiyun'TOP pins'. For pins like KEY_ROW2, the pinmux is controlled by both 39*4882a593SmuzhiyunTOP_PMM and AON_IOCFG blocks, as the available multiplexing functions for 40*4882a593Smuzhiyunthe pin spread in both controllers. This type of pins are called 'AON pins'. 41*4882a593SmuzhiyunThough pinmux implementation is quite different, pinconf is same for both 42*4882a593Smuzhiyuntypes of pins. Both are controlled by auxiliary controller, i.e. AON_IOCFG 43*4882a593Smuzhiyunon ZX296718. 44*4882a593Smuzhiyun 45*4882a593SmuzhiyunRequired properties: 46*4882a593Smuzhiyun- compatible: should be "zte,zx296718-pmm". 47*4882a593Smuzhiyun- reg: the register physical address and length. 48*4882a593Smuzhiyun- zte,auxiliary-controller: phandle to the auxiliary pin controller which 49*4882a593Smuzhiyun implements pinmux for AON pins and pinconf for all pins. 50*4882a593Smuzhiyun 51*4882a593SmuzhiyunThe following pin configuration are supported. Please refer to 52*4882a593Smuzhiyunpinctrl-bindings.txt in this directory for more details of the common 53*4882a593Smuzhiyunpinctrl bindings used by client devices. 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun- bias-pull-up 56*4882a593Smuzhiyun- bias-pull-down 57*4882a593Smuzhiyun- drive-strength 58*4882a593Smuzhiyun- input-enable 59*4882a593Smuzhiyun- slew-rate 60*4882a593Smuzhiyun 61*4882a593SmuzhiyunExamples: 62*4882a593Smuzhiyun 63*4882a593Smuzhiyuniocfg: pin-controller@119000 { 64*4882a593Smuzhiyun compatible = "zte,zx296718-iocfg"; 65*4882a593Smuzhiyun reg = <0x119000 0x1000>; 66*4882a593Smuzhiyun}; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyunpmm: pin-controller@1462000 { 69*4882a593Smuzhiyun compatible = "zte,zx296718-pmm"; 70*4882a593Smuzhiyun reg = <0x1462000 0x1000>; 71*4882a593Smuzhiyun zte,auxiliary-controller = <&iocfg>; 72*4882a593Smuzhiyun}; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun&pmm { 75*4882a593Smuzhiyun vga_pins: vga { 76*4882a593Smuzhiyun pins = "KEY_COL1", "KEY_COL2", "KEY_ROW1", "KEY_ROW2"; 77*4882a593Smuzhiyun function = "VGA"; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun}; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun&vga { 82*4882a593Smuzhiyun pinctrl-names = "default"; 83*4882a593Smuzhiyun pinctrl-0 = <&vga_pins>; 84*4882a593Smuzhiyun}; 85