1*4882a593SmuzhiyunVIA VT8500 and Wondermedia WM8xxx-series pinmux/gpio controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThese SoCs contain a combined Pinmux/GPIO module. Each pin may operate as 4*4882a593Smuzhiyuneither a GPIO in, GPIO out or as an alternate function (I2C, SPI etc). 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible: "via,vt8500-pinctrl", "wm,wm8505-pinctrl", "wm,wm8650-pinctrl", 8*4882a593Smuzhiyun "wm8750-pinctrl" or "wm,wm8850-pinctrl" 9*4882a593Smuzhiyun- reg: Should contain the physical address of the module's registers. 10*4882a593Smuzhiyun- interrupt-controller: Marks the device node as an interrupt controller. 11*4882a593Smuzhiyun- #interrupt-cells: Should be two. 12*4882a593Smuzhiyun- gpio-controller: Marks the device node as a GPIO controller. 13*4882a593Smuzhiyun- #gpio-cells : Should be two. The first cell is the pin number and the 14*4882a593Smuzhiyun second cell is used to specify optional parameters. 15*4882a593Smuzhiyun bit 0 - active low 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunPlease refer to ../gpio/gpio.txt for a general description of GPIO bindings. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunPlease refer to pinctrl-bindings.txt in this directory for details of the 20*4882a593Smuzhiyuncommon pinctrl bindings used by client devices, including the meaning of the 21*4882a593Smuzhiyunphrase "pin configuration node". 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunEach pin configuration node lists the pin(s) to which it applies, and one or 24*4882a593Smuzhiyunmore of the mux functions to select on those pin(s), and pull-up/down 25*4882a593Smuzhiyunconfiguration. Each subnode only affects those parameters that are explicitly 26*4882a593Smuzhiyunlisted. In other words, a subnode that lists only a mux function implies no 27*4882a593Smuzhiyuninformation about any pull configuration. Similarly, a subnode that lists only 28*4882a593Smuzhiyuna pull parameter implies no information about the mux function. 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunRequired subnode-properties: 31*4882a593Smuzhiyun- wm,pins: An array of cells. Each cell contains the ID of a pin. 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunOptional subnode-properties: 34*4882a593Smuzhiyun- wm,function: Integer, containing the function to mux to the pin(s): 35*4882a593Smuzhiyun 0: GPIO in 36*4882a593Smuzhiyun 1: GPIO out 37*4882a593Smuzhiyun 2: alternate 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun- wm,pull: Integer, representing the pull-down/up to apply to the pin(s): 40*4882a593Smuzhiyun 0: none 41*4882a593Smuzhiyun 1: down 42*4882a593Smuzhiyun 2: up 43*4882a593Smuzhiyun 44*4882a593SmuzhiyunEach of wm,function and wm,pull may contain either a single value which 45*4882a593Smuzhiyunwill be applied to all pins in wm,pins, or one value for each entry in 46*4882a593Smuzhiyunwm,pins. 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunExample: 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun pinctrl: pinctrl { 51*4882a593Smuzhiyun compatible = "wm,wm8505-pinctrl"; 52*4882a593Smuzhiyun reg = <0xD8110000 0x10000>; 53*4882a593Smuzhiyun interrupt-controller; 54*4882a593Smuzhiyun #interrupt-cells = <2>; 55*4882a593Smuzhiyun gpio-controller; 56*4882a593Smuzhiyun #gpio-cells = <2>; 57*4882a593Smuzhiyun }; 58