1*4882a593SmuzhiyunPalmas Pincontrol bindings 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe pins of Palmas device can be set on different option and provides 4*4882a593Smuzhiyunthe configuration for Pull UP/DOWN, open drain etc. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible: It must be one of following: 8*4882a593Smuzhiyun - "ti,palmas-pinctrl" for Palma series of the pincontrol. 9*4882a593Smuzhiyun - "ti,tps65913-pinctrl" for Palma series device TPS65913. 10*4882a593Smuzhiyun - "ti,tps80036-pinctrl" for Palma series device TPS80036. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunPlease refer to pinctrl-bindings.txt in this directory for details of the 13*4882a593Smuzhiyuncommon pinctrl bindings used by client devices, including the meaning of the 14*4882a593Smuzhiyunphrase "pin configuration node". 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunPalmas's pin configuration nodes act as a container for an arbitrary number of 17*4882a593Smuzhiyunsubnodes. Each of these subnodes represents some desired configuration for a 18*4882a593Smuzhiyunlist of pins. This configuration can include the mux function to select on 19*4882a593Smuzhiyunthose pin(s), and various pin configuration parameters, such as pull-up, 20*4882a593Smuzhiyunopen drain. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunThe name of each subnode is not important; all subnodes should be enumerated 23*4882a593Smuzhiyunand processed purely based on their content. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunEach subnode only affects those parameters that are explicitly listed. In 26*4882a593Smuzhiyunother words, a subnode that lists a mux function but no pin configuration 27*4882a593Smuzhiyunparameters implies no information about any pin configuration parameters. 28*4882a593SmuzhiyunSimilarly, a pin subnode that describes a pullup parameter implies no 29*4882a593Smuzhiyuninformation about e.g. the mux function. 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunOptional properties: 32*4882a593Smuzhiyun- ti,palmas-enable-dvfs1: Enable DVFS1. Configure pins for DVFS1 mode. 33*4882a593Smuzhiyun Selection primary or secondary function associated to I2C2_SCL_SCE, 34*4882a593Smuzhiyun I2C2_SDA_SDO pin/pad for DVFS1 interface 35*4882a593Smuzhiyun- ti,palmas-enable-dvfs2: Enable DVFS2. Configure pins for DVFS2 mode. 36*4882a593Smuzhiyun Selection primary or secondary function associated to GPADC_START 37*4882a593Smuzhiyun and SYSEN2 pin/pad for DVFS2 interface 38*4882a593Smuzhiyun- ti,palmas-override-powerhold: This is applicable for PMICs for which 39*4882a593Smuzhiyun GPIO7 is configured in POWERHOLD mode which has higher priority 40*4882a593Smuzhiyun over DEV_ON bit and keeps the PMIC supplies on even after the DEV_ON 41*4882a593Smuzhiyun bit is turned off. This property enables driver to over ride the 42*4882a593Smuzhiyun POWERHOLD value to GPIO7 so as to turn off the PMIC in power off 43*4882a593Smuzhiyun scenarios. So for GPIO7 if ti,palmas-override-powerhold is set 44*4882a593Smuzhiyun then the GPIO_7 field should never be muxed to anything else. 45*4882a593Smuzhiyun It should be set to POWERHOLD by default and only in case of 46*4882a593Smuzhiyun power off scenarios the driver will over ride the mux value. 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunThis binding uses the following generic properties as defined in 49*4882a593Smuzhiyunpinctrl-bindings.txt: 50*4882a593Smuzhiyun 51*4882a593SmuzhiyunRequired: pins 52*4882a593SmuzhiyunOptions: function, bias-disable, bias-pull-up, bias-pull-down, 53*4882a593Smuzhiyun drive-open-drain. 54*4882a593Smuzhiyun 55*4882a593SmuzhiyunNote that many of these properties are only valid for certain specific pins. 56*4882a593SmuzhiyunSee the Palmas device datasheet for complete details regarding which pins 57*4882a593Smuzhiyunsupport which functionality. 58*4882a593Smuzhiyun 59*4882a593SmuzhiyunValid values for pin names are: 60*4882a593Smuzhiyun gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8, gpio9, 61*4882a593Smuzhiyun gpio10, gpio11, gpio12, gpio13, gpio14, gpio15, vac, powergood, 62*4882a593Smuzhiyun nreswarm, pwrdown, gpadc_start, reset_in, nsleep, enable1, enable2, 63*4882a593Smuzhiyun int. 64*4882a593Smuzhiyun 65*4882a593SmuzhiyunValid value of function names are: 66*4882a593Smuzhiyun gpio, led, pwm, regen, sysen, clk32kgaudio, id, vbus_det, chrg_det, 67*4882a593Smuzhiyun vac, vacok, powergood, usb_psel, msecure, pwrhold, int, nreswarm, 68*4882a593Smuzhiyun simrsto, simrsti, low_vbat, wireless_chrg1, rcm, pwrdown, gpadc_start, 69*4882a593Smuzhiyun reset_in, nsleep, enable. 70*4882a593Smuzhiyun 71*4882a593SmuzhiyunThere are 4 special functions: opt0, opt1, opt2 and opt3. If any of these 72*4882a593Smuzhiyunfunctions is selected then directly pins register will be written with 0, 1, 2 73*4882a593Smuzhiyunor 3 respectively if it is valid for that pins or list of pins. 74*4882a593Smuzhiyun 75*4882a593SmuzhiyunExample: 76*4882a593Smuzhiyun palmas: tps65913 { 77*4882a593Smuzhiyun .... 78*4882a593Smuzhiyun pinctrl { 79*4882a593Smuzhiyun compatible = "ti,tps65913-pinctrl"; 80*4882a593Smuzhiyun ti,palmas-enable-dvfs1; 81*4882a593Smuzhiyun pinctrl-names = "default"; 82*4882a593Smuzhiyun pinctrl-0 = <&palmas_pins_state>; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun palmas_pins_state: pinmux { 85*4882a593Smuzhiyun gpio0 { 86*4882a593Smuzhiyun pins = "gpio0"; 87*4882a593Smuzhiyun function = "id"; 88*4882a593Smuzhiyun bias-pull-up; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun vac { 92*4882a593Smuzhiyun pins = "vac"; 93*4882a593Smuzhiyun function = "vacok"; 94*4882a593Smuzhiyun bias-pull-down; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun gpio5 { 98*4882a593Smuzhiyun pins = "gpio5"; 99*4882a593Smuzhiyun function = "opt0"; 100*4882a593Smuzhiyun drive-open-drain = <1>; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun .... 105*4882a593Smuzhiyun }; 106