xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/pinctrl-mt6797.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun* MediaTek MT6797 Pin Controller
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunThe MediaTek's MT6797 Pin controller is used to control SoC pins.
4*4882a593Smuzhiyun
5*4882a593SmuzhiyunRequired properties:
6*4882a593Smuzhiyun- compatible: Value should be one of the following.
7*4882a593Smuzhiyun              "mediatek,mt6797-pinctrl", compatible with mt6797 pinctrl.
8*4882a593Smuzhiyun- reg:        Should contain address and size for gpio, iocfgl, iocfgb,
9*4882a593Smuzhiyun              iocfgr and iocfgt register bases.
10*4882a593Smuzhiyun- reg-names:  An array of strings describing the "reg" entries. Must
11*4882a593Smuzhiyun              contain "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt".
12*4882a593Smuzhiyun- gpio-controller: Marks the device node as a gpio controller.
13*4882a593Smuzhiyun- #gpio-cells: Should be two. The first cell is the gpio pin number
14*4882a593Smuzhiyun               and the second cell is used for optional parameters.
15*4882a593Smuzhiyun
16*4882a593SmuzhiyunOptional properties:
17*4882a593Smuzhiyun- interrupt-controller: Marks the device node as an interrupt controller.
18*4882a593Smuzhiyun- #interrupt-cells: Should be two.
19*4882a593Smuzhiyun- interrupts : The interrupt outputs from the controller.
20*4882a593Smuzhiyun
21*4882a593SmuzhiyunPlease refer to pinctrl-bindings.txt in this directory for details of the
22*4882a593Smuzhiyuncommon pinctrl bindings used by client devices.
23*4882a593Smuzhiyun
24*4882a593SmuzhiyunSubnode format
25*4882a593SmuzhiyunA pinctrl node should contain at least one subnodes representing the
26*4882a593Smuzhiyunpinctrl groups available on the machine. Each subnode will list the
27*4882a593Smuzhiyunpins it needs, and how they should be configured, with regard to muxer
28*4882a593Smuzhiyunconfiguration, pullups, drive strength, input enable/disable and input schmitt.
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun    node {
31*4882a593Smuzhiyun        pinmux = <PIN_NUMBER_PINMUX>;
32*4882a593Smuzhiyun        GENERIC_PINCONFIG;
33*4882a593Smuzhiyun    };
34*4882a593Smuzhiyun
35*4882a593SmuzhiyunRequired properties:
36*4882a593Smuzhiyun- pinmux: Integer array, represents gpio pin number and mux setting.
37*4882a593Smuzhiyun    Supported pin number and mux varies for different SoCs, and are defined
38*4882a593Smuzhiyun    as macros in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
39*4882a593Smuzhiyun
40*4882a593SmuzhiyunOptional properties:
41*4882a593Smuzhiyun- GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
42*4882a593Smuzhiyun    bias-pull, bias-pull-down, input-enable, input-schmitt-enable,
43*4882a593Smuzhiyun    input-schmitt-disable, output-enable output-low, output-high,
44*4882a593Smuzhiyun    drive-strength, and slew-rate are valid.
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun    Valid arguments for 'slew-rate' are '0' for no slew rate controlled and
47*4882a593Smuzhiyun    '1' for slower slew rate respectively. Valid arguments for 'drive-strength'
48*4882a593Smuzhiyun    is limited, such as 2, 4, 8, 12, or 16 in mA.
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun    Some optional vendor properties as defined are valid to specify in a
51*4882a593Smuzhiyun    pinconf subnode:
52*4882a593Smuzhiyun    - mediatek,tdsel: An integer describing the steps for output level shifter
53*4882a593Smuzhiyun      duty cycle when asserted (high pulse width adjustment). Valid arguments
54*4882a593Smuzhiyun      are from 0 to 15.
55*4882a593Smuzhiyun    - mediatek,rdsel: An integer describing the steps for input level shifter
56*4882a593Smuzhiyun      duty cycle when asserted (high pulse width adjustment). Valid arguments
57*4882a593Smuzhiyun      are from 0 to 63.
58*4882a593Smuzhiyun    - mediatek,pull-up-adv: An integer describing the code R1R0 as 0, 1, 2
59*4882a593Smuzhiyun      or 3 for the advanced pull-up resistors.
60*4882a593Smuzhiyun    - mediatek,pull-down-adv: An integer describing the code R1R0 as 0, 1, 2,
61*4882a593Smuzhiyun      or 3 for the advanced pull-down resistors.
62*4882a593Smuzhiyun
63*4882a593SmuzhiyunExamples:
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun        pio: pinctrl@10005000 {
66*4882a593Smuzhiyun                compatible = "mediatek,mt6797-pinctrl";
67*4882a593Smuzhiyun                reg = <0 0x10005000 0 0x1000>,
68*4882a593Smuzhiyun                      <0 0x10002000 0 0x400>,
69*4882a593Smuzhiyun                      <0 0x10002400 0 0x400>,
70*4882a593Smuzhiyun                      <0 0x10002800 0 0x400>,
71*4882a593Smuzhiyun                      <0 0x10002C00 0 0x400>;
72*4882a593Smuzhiyun                reg-names = "gpio", "iocfgl", "iocfgb",
73*4882a593Smuzhiyun                            "iocfgr", "iocfgt";
74*4882a593Smuzhiyun                gpio-controller;
75*4882a593Smuzhiyun                #gpio-cells = <2>;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun                uart1_pins_a: uart1 {
78*4882a593Smuzhiyun                        pins1 {
79*4882a593Smuzhiyun                                pinmux = <MT6797_GPIO232__FUNC_URXD1>,
80*4882a593Smuzhiyun                                         <MT6797_GPIO233__FUNC_UTXD1>;
81*4882a593Smuzhiyun                        };
82*4882a593Smuzhiyun                };
83*4882a593Smuzhiyun        };
84