xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/pinctrl-mcp23s08.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunMicrochip MCP2308/MCP23S08/MCP23017/MCP23S17 driver for
2*4882a593Smuzhiyun8-/16-bit I/O expander with serial interface (I2C/SPI)
3*4882a593Smuzhiyun
4*4882a593SmuzhiyunRequired properties:
5*4882a593Smuzhiyun- compatible : Should be
6*4882a593Smuzhiyun    - "mcp,mcp23s08" (DEPRECATED) for  8 GPIO SPI version
7*4882a593Smuzhiyun    - "mcp,mcp23s17" (DEPRECATED) for 16 GPIO SPI version
8*4882a593Smuzhiyun    - "mcp,mcp23008" (DEPRECATED) for  8 GPIO I2C version or
9*4882a593Smuzhiyun    - "mcp,mcp23017" (DEPRECATED) for 16 GPIO I2C version of the chip
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun    - "microchip,mcp23s08" for  8 GPIO SPI version
12*4882a593Smuzhiyun    - "microchip,mcp23s17" for 16 GPIO SPI version
13*4882a593Smuzhiyun    - "microchip,mcp23s18" for 16 GPIO SPI version
14*4882a593Smuzhiyun    - "microchip,mcp23008" for  8 GPIO I2C version or
15*4882a593Smuzhiyun    - "microchip,mcp23017" for 16 GPIO I2C version of the chip
16*4882a593Smuzhiyun    - "microchip,mcp23018" for 16 GPIO I2C version
17*4882a593Smuzhiyun    NOTE: Do not use the old mcp prefix any more. It is deprecated and will be
18*4882a593Smuzhiyun    removed.
19*4882a593Smuzhiyun- #gpio-cells : Should be two.
20*4882a593Smuzhiyun  - first cell is the pin number
21*4882a593Smuzhiyun  - second cell is used to specify flags as described in
22*4882a593Smuzhiyun    'Documentation/devicetree/bindings/gpio/gpio.txt'. Allowed values defined by
23*4882a593Smuzhiyun    'include/dt-bindings/gpio/gpio.h' (e.g. GPIO_ACTIVE_LOW).
24*4882a593Smuzhiyun- gpio-controller : Marks the device node as a GPIO controller.
25*4882a593Smuzhiyun- reg : For an address on its bus. I2C uses this a the I2C address of the chip.
26*4882a593Smuzhiyun        SPI uses this to specify the chipselect line which the chip is
27*4882a593Smuzhiyun        connected to. The driver and the SPI variant of the chip support
28*4882a593Smuzhiyun        multiple chips on the same chipselect. Have a look at
29*4882a593Smuzhiyun        microchip,spi-present-mask below.
30*4882a593Smuzhiyun
31*4882a593SmuzhiyunRequired device specific properties (only for SPI chips):
32*4882a593Smuzhiyun- mcp,spi-present-mask (DEPRECATED)
33*4882a593Smuzhiyun- microchip,spi-present-mask : This is a present flag, that makes only sense for SPI
34*4882a593Smuzhiyun        chips - as the name suggests. Multiple SPI chips can share the same
35*4882a593Smuzhiyun        SPI chipselect. Set a bit in bit0-7 in this mask to 1 if there is a
36*4882a593Smuzhiyun        chip connected with the corresponding spi address set. For example if
37*4882a593Smuzhiyun        you have a chip with address 3 connected, you have to set bit3 to 1,
38*4882a593Smuzhiyun        which is 0x08. mcp23s08 chip variant only supports bits 0-3. It is not
39*4882a593Smuzhiyun        possible to mix mcp23s08 and mcp23s17 on the same chipselect. Set at
40*4882a593Smuzhiyun        least one bit to 1 for SPI chips.
41*4882a593Smuzhiyun    NOTE: Do not use the old mcp prefix any more. It is deprecated and will be
42*4882a593Smuzhiyun    removed.
43*4882a593Smuzhiyun- spi-max-frequency = The maximum frequency this chip is able to handle
44*4882a593Smuzhiyun
45*4882a593SmuzhiyunOptional properties:
46*4882a593Smuzhiyun- #interrupt-cells : Should be two.
47*4882a593Smuzhiyun  - first cell is the pin number
48*4882a593Smuzhiyun  - second cell is used to specify flags.
49*4882a593Smuzhiyun- interrupt-controller: Marks the device node as a interrupt controller.
50*4882a593Smuzhiyun- drive-open-drain: Sets the ODR flag in the IOCON register. This configures
51*4882a593Smuzhiyun        the IRQ output as open drain active low.
52*4882a593Smuzhiyun
53*4882a593SmuzhiyunOptional device specific properties:
54*4882a593Smuzhiyun- microchip,irq-mirror: Sets the mirror flag in the IOCON register. Devices
55*4882a593Smuzhiyun        with two interrupt outputs (these are the devices ending with 17 and
56*4882a593Smuzhiyun        those that have 16 IOs) have two IO banks: IO 0-7 form bank 1 and
57*4882a593Smuzhiyun        IO 8-15 are bank 2. These chips have two different interrupt outputs:
58*4882a593Smuzhiyun        One for bank 1 and another for bank 2. If irq-mirror is set, both
59*4882a593Smuzhiyun        interrupts are generated regardless of the bank that an input change
60*4882a593Smuzhiyun        occurred on. If it is not set, the interrupt are only generated for the
61*4882a593Smuzhiyun        bank they belong to.
62*4882a593Smuzhiyun        On devices with only one interrupt output this property is useless.
63*4882a593Smuzhiyun- microchip,irq-active-high: Sets the INTPOL flag in the IOCON register. This
64*4882a593Smuzhiyun        configures the IRQ output polarity as active high.
65*4882a593Smuzhiyun
66*4882a593SmuzhiyunExample I2C (with interrupt):
67*4882a593Smuzhiyungpiom1: gpio@20 {
68*4882a593Smuzhiyun        compatible = "microchip,mcp23017";
69*4882a593Smuzhiyun        gpio-controller;
70*4882a593Smuzhiyun        #gpio-cells = <2>;
71*4882a593Smuzhiyun        reg = <0x20>;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun        interrupt-parent = <&gpio1>;
74*4882a593Smuzhiyun        interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
75*4882a593Smuzhiyun        interrupt-controller;
76*4882a593Smuzhiyun        #interrupt-cells=<2>;
77*4882a593Smuzhiyun        microchip,irq-mirror;
78*4882a593Smuzhiyun};
79*4882a593Smuzhiyun
80*4882a593SmuzhiyunExample SPI:
81*4882a593Smuzhiyungpiom1: gpio@0 {
82*4882a593Smuzhiyun        compatible = "microchip,mcp23s17";
83*4882a593Smuzhiyun        gpio-controller;
84*4882a593Smuzhiyun        #gpio-cells = <2>;
85*4882a593Smuzhiyun        microchip,spi-present-mask = <0x01>;
86*4882a593Smuzhiyun        reg = <0>;
87*4882a593Smuzhiyun        spi-max-frequency = <1000000>;
88*4882a593Smuzhiyun};
89*4882a593Smuzhiyun
90*4882a593SmuzhiyunPull-up configuration
91*4882a593Smuzhiyun=====================
92*4882a593Smuzhiyun
93*4882a593SmuzhiyunIf pins are used as output, they can also be configured with pull-ups. This is
94*4882a593Smuzhiyundone with pinctrl.
95*4882a593Smuzhiyun
96*4882a593SmuzhiyunPlease refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
97*4882a593Smuzhiyunfor details of the common pinctrl bindings used by client devices,
98*4882a593Smuzhiyunincluding the meaning of the phrase "pin configuration node".
99*4882a593Smuzhiyun
100*4882a593SmuzhiyunOptional Pinmux properties:
101*4882a593Smuzhiyun--------------------------
102*4882a593SmuzhiyunFollowing properties are required if default setting of pins are required
103*4882a593Smuzhiyunat boot.
104*4882a593Smuzhiyun- pinctrl-names: A pinctrl state named per <pinctrl-bindings.txt>.
105*4882a593Smuzhiyun- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
106*4882a593Smuzhiyun		<pinctrl-bindings.txt>.
107*4882a593Smuzhiyun
108*4882a593SmuzhiyunThe pin configurations are defined as child of the pinctrl states node. Each
109*4882a593Smuzhiyunsub-node have following properties:
110*4882a593Smuzhiyun
111*4882a593SmuzhiyunRequired properties:
112*4882a593Smuzhiyun------------------
113*4882a593Smuzhiyun- pins: List of pins. Valid values of pins properties are:
114*4882a593Smuzhiyun		      gpio0 ... gpio7 for the devices with 8 GPIO pins and
115*4882a593Smuzhiyun		      gpio0 ... gpio15 for the devices with 16 GPIO pins.
116*4882a593Smuzhiyun
117*4882a593SmuzhiyunOptional properties:
118*4882a593Smuzhiyun-------------------
119*4882a593SmuzhiyunThe following optional property is defined in the pinmux DT binding document
120*4882a593Smuzhiyun<pinctrl-bindings.txt>. Absence of this property will leave the configuration
121*4882a593Smuzhiyunin its default state.
122*4882a593Smuzhiyun	bias-pull-up
123*4882a593Smuzhiyun
124*4882a593SmuzhiyunExample with pinctrl to pull-up output pins:
125*4882a593Smuzhiyungpio21: gpio@21 {
126*4882a593Smuzhiyun	compatible = "microchip,mcp23017";
127*4882a593Smuzhiyun	gpio-controller;
128*4882a593Smuzhiyun	#gpio-cells = <0x2>;
129*4882a593Smuzhiyun	reg = <0x21>;
130*4882a593Smuzhiyun	interrupt-parent = <&socgpio>;
131*4882a593Smuzhiyun	interrupts = <0x17 0x8>;
132*4882a593Smuzhiyun	interrupt-names = "mcp23017@21 irq";
133*4882a593Smuzhiyun	interrupt-controller;
134*4882a593Smuzhiyun	#interrupt-cells = <0x2>;
135*4882a593Smuzhiyun	microchip,irq-mirror;
136*4882a593Smuzhiyun	pinctrl-names = "default";
137*4882a593Smuzhiyun	pinctrl-0 = <&i2cgpio0irq &gpio21pullups>;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun	gpio21pullups: pinmux {
140*4882a593Smuzhiyun		pins =	"gpio0", "gpio1", "gpio2", "gpio3",
141*4882a593Smuzhiyun			"gpio4", "gpio5", "gpio6", "gpio7",
142*4882a593Smuzhiyun			"gpio8", "gpio9", "gpio10", "gpio11",
143*4882a593Smuzhiyun			"gpio12", "gpio13", "gpio14", "gpio15";
144*4882a593Smuzhiyun		bias-pull-up;
145*4882a593Smuzhiyun	};
146*4882a593Smuzhiyun};
147