1*4882a593Smuzhiyun== Introduction == 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunHardware modules that control pin multiplexing or configuration parameters 4*4882a593Smuzhiyunsuch as pull-up/down, tri-state, drive-strength etc are designated as pin 5*4882a593Smuzhiyuncontrollers. Each pin controller must be represented as a node in device tree, 6*4882a593Smuzhiyunjust like any other hardware module. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunHardware modules whose signals are affected by pin configuration are 9*4882a593Smuzhiyundesignated client devices. Again, each client device must be represented as a 10*4882a593Smuzhiyunnode in device tree, just like any other hardware module. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunFor a client device to operate correctly, certain pin controllers must 13*4882a593Smuzhiyunset up certain specific pin configurations. Some client devices need a 14*4882a593Smuzhiyunsingle static pin configuration, e.g. set up during initialization. Others 15*4882a593Smuzhiyunneed to reconfigure pins at run-time, for example to tri-state pins when the 16*4882a593Smuzhiyundevice is inactive. Hence, each client device can define a set of named 17*4882a593Smuzhiyunstates. The number and names of those states is defined by the client device's 18*4882a593Smuzhiyunown binding. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunThe common pinctrl bindings defined in this file provide an infrastructure 21*4882a593Smuzhiyunfor client device device tree nodes to map those state names to the pin 22*4882a593Smuzhiyunconfiguration used by those states. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunNote that pin controllers themselves may also be client devices of themselves. 25*4882a593SmuzhiyunFor example, a pin controller may set up its own "active" state when the 26*4882a593Smuzhiyundriver loads. This would allow representing a board's static pin configuration 27*4882a593Smuzhiyunin a single place, rather than splitting it across multiple client device 28*4882a593Smuzhiyunnodes. The decision to do this or not somewhat rests with the author of 29*4882a593Smuzhiyunindividual board device tree files, and any requirements imposed by the 30*4882a593Smuzhiyunbindings for the individual client devices in use by that board, i.e. whether 31*4882a593Smuzhiyunthey require certain specific named states for dynamic pin configuration. 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun== Pinctrl client devices == 34*4882a593Smuzhiyun 35*4882a593SmuzhiyunFor each client device individually, every pin state is assigned an integer 36*4882a593SmuzhiyunID. These numbers start at 0, and are contiguous. For each state ID, a unique 37*4882a593Smuzhiyunproperty exists to define the pin configuration. Each state may also be 38*4882a593Smuzhiyunassigned a name. When names are used, another property exists to map from 39*4882a593Smuzhiyunthose names to the integer IDs. 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunEach client device's own binding determines the set of states that must be 42*4882a593Smuzhiyundefined in its device tree node, and whether to define the set of state 43*4882a593SmuzhiyunIDs that must be provided, or whether to define the set of state names that 44*4882a593Smuzhiyunmust be provided. 45*4882a593Smuzhiyun 46*4882a593SmuzhiyunRequired properties: 47*4882a593Smuzhiyunpinctrl-0: List of phandles, each pointing at a pin configuration 48*4882a593Smuzhiyun node. These referenced pin configuration nodes must be child 49*4882a593Smuzhiyun nodes of the pin controller that they configure. Multiple 50*4882a593Smuzhiyun entries may exist in this list so that multiple pin 51*4882a593Smuzhiyun controllers may be configured, or so that a state may be built 52*4882a593Smuzhiyun from multiple nodes for a single pin controller, each 53*4882a593Smuzhiyun contributing part of the overall configuration. See the next 54*4882a593Smuzhiyun section of this document for details of the format of these 55*4882a593Smuzhiyun pin configuration nodes. 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun In some cases, it may be useful to define a state, but for it 58*4882a593Smuzhiyun to be empty. This may be required when a common IP block is 59*4882a593Smuzhiyun used in an SoC either without a pin controller, or where the 60*4882a593Smuzhiyun pin controller does not affect the HW module in question. If 61*4882a593Smuzhiyun the binding for that IP block requires certain pin states to 62*4882a593Smuzhiyun exist, they must still be defined, but may be left empty. 63*4882a593Smuzhiyun 64*4882a593SmuzhiyunOptional properties: 65*4882a593Smuzhiyunpinctrl-1: List of phandles, each pointing at a pin configuration 66*4882a593Smuzhiyun node within a pin controller. 67*4882a593Smuzhiyun... 68*4882a593Smuzhiyunpinctrl-n: List of phandles, each pointing at a pin configuration 69*4882a593Smuzhiyun node within a pin controller. 70*4882a593Smuzhiyunpinctrl-names: The list of names to assign states. List entry 0 defines the 71*4882a593Smuzhiyun name for integer state ID 0, list entry 1 for state ID 1, and 72*4882a593Smuzhiyun so on. 73*4882a593Smuzhiyun 74*4882a593SmuzhiyunFor example: 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* For a client device requiring named states */ 77*4882a593Smuzhiyun device { 78*4882a593Smuzhiyun pinctrl-names = "active", "idle"; 79*4882a593Smuzhiyun pinctrl-0 = <&state_0_node_a>; 80*4882a593Smuzhiyun pinctrl-1 = <&state_1_node_a &state_1_node_b>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* For the same device if using state IDs */ 84*4882a593Smuzhiyun device { 85*4882a593Smuzhiyun pinctrl-0 = <&state_0_node_a>; 86*4882a593Smuzhiyun pinctrl-1 = <&state_1_node_a &state_1_node_b>; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* 90*4882a593Smuzhiyun * For an IP block whose binding supports pin configuration, 91*4882a593Smuzhiyun * but in use on an SoC that doesn't have any pin control hardware 92*4882a593Smuzhiyun */ 93*4882a593Smuzhiyun device { 94*4882a593Smuzhiyun pinctrl-names = "active", "idle"; 95*4882a593Smuzhiyun pinctrl-0 = <>; 96*4882a593Smuzhiyun pinctrl-1 = <>; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun== Pin controller devices == 100*4882a593SmuzhiyunRequired properties: See the pin controller driver specific documentation 101*4882a593Smuzhiyun 102*4882a593SmuzhiyunOptional properties: 103*4882a593Smuzhiyun#pinctrl-cells: Number of pin control cells in addition to the index within the 104*4882a593Smuzhiyun pin controller device instance 105*4882a593Smuzhiyun 106*4882a593Smuzhiyunpinctrl-use-default: Boolean. Indicates that the OS can use the boot default 107*4882a593Smuzhiyun pin configuration. This allows using an OS that does not have a 108*4882a593Smuzhiyun driver for the pin controller. This property can be set either 109*4882a593Smuzhiyun globally for the pin controller or in child nodes for individual 110*4882a593Smuzhiyun pin group control. 111*4882a593Smuzhiyun 112*4882a593SmuzhiyunPin controller devices should contain the pin configuration nodes that client 113*4882a593Smuzhiyundevices reference. 114*4882a593Smuzhiyun 115*4882a593SmuzhiyunFor example: 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun pincontroller { 118*4882a593Smuzhiyun ... /* Standard DT properties for the device itself elided */ 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun state_0_node_a { 121*4882a593Smuzhiyun ... 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun state_1_node_a { 124*4882a593Smuzhiyun ... 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun state_1_node_b { 127*4882a593Smuzhiyun ... 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun } 130*4882a593Smuzhiyun 131*4882a593SmuzhiyunThe contents of each of those pin configuration child nodes is defined 132*4882a593Smuzhiyunentirely by the binding for the individual pin controller device. There 133*4882a593Smuzhiyunexists no common standard for this content. The pinctrl framework only 134*4882a593Smuzhiyunprovides generic helper bindings that the pin controller driver can use. 135*4882a593Smuzhiyun 136*4882a593SmuzhiyunThe pin configuration nodes need not be direct children of the pin controller 137*4882a593Smuzhiyundevice; they may be grandchildren, for example. Whether this is legal, and 138*4882a593Smuzhiyunwhether there is any interaction between the child and intermediate parent 139*4882a593Smuzhiyunnodes, is again defined entirely by the binding for the individual pin 140*4882a593Smuzhiyuncontroller device. 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun== Generic pin multiplexing node content == 143*4882a593Smuzhiyun 144*4882a593SmuzhiyunSee pinmux-node.yaml 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun== Generic pin configuration node content == 147*4882a593Smuzhiyun 148*4882a593SmuzhiyunSee pincfg-node.yaml 149