1*4882a593SmuzhiyunNXP LPC18xx/43xx SCU pin controller Device Tree Bindings 2*4882a593Smuzhiyun-------------------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- compatible : Should be "nxp,lpc1850-scu" 6*4882a593Smuzhiyun- reg : Address and length of the register set for the device 7*4882a593Smuzhiyun- clocks : Clock specifier (see clock bindings for details) 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunThe lpc1850-scu driver uses the generic pin multiplexing and generic pin 10*4882a593Smuzhiyunconfiguration documented in pinctrl-bindings.txt. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunThe following generic nodes are supported: 13*4882a593Smuzhiyun - function 14*4882a593Smuzhiyun - pins 15*4882a593Smuzhiyun - bias-disable 16*4882a593Smuzhiyun - bias-pull-up 17*4882a593Smuzhiyun - bias-pull-down 18*4882a593Smuzhiyun - drive-strength 19*4882a593Smuzhiyun - input-enable 20*4882a593Smuzhiyun - input-disable 21*4882a593Smuzhiyun - input-schmitt-enable 22*4882a593Smuzhiyun - input-schmitt-disable 23*4882a593Smuzhiyun - slew-rate 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunNXP specific properties: 26*4882a593Smuzhiyun - nxp,gpio-pin-interrupt : Assign pin to gpio pin interrupt controller 27*4882a593Smuzhiyun irq number 0 to 7. See example below. 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunNot all pins support all properties so either refer to the NXP 1850/4350 30*4882a593Smuzhiyunuser manual or the pin table in the pinctrl-lpc18xx driver for supported 31*4882a593Smuzhiyunpin properties. 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunExample: 34*4882a593Smuzhiyunpinctrl: pinctrl@40086000 { 35*4882a593Smuzhiyun compatible = "nxp,lpc1850-scu"; 36*4882a593Smuzhiyun reg = <0x40086000 0x1000>; 37*4882a593Smuzhiyun clocks = <&ccu1 CLK_CPU_SCU>; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun i2c0_pins: i2c0-pins { 40*4882a593Smuzhiyun i2c0_pins_cfg { 41*4882a593Smuzhiyun pins = "i2c0_scl", "i2c0_sda"; 42*4882a593Smuzhiyun function = "i2c0"; 43*4882a593Smuzhiyun input-enable; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun uart0_pins: uart0-pins { 48*4882a593Smuzhiyun uart0_rx_cfg { 49*4882a593Smuzhiyun pins = "pf_11"; 50*4882a593Smuzhiyun function = "uart0"; 51*4882a593Smuzhiyun bias-disable; 52*4882a593Smuzhiyun input-enable; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun uart0_tx_cfg { 56*4882a593Smuzhiyun pins = "pf_10"; 57*4882a593Smuzhiyun function = "uart0"; 58*4882a593Smuzhiyun bias-disable; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun gpio_joystick_pins: gpio-joystick-pins { 63*4882a593Smuzhiyun gpio_joystick_1_cfg { 64*4882a593Smuzhiyun pins = "p9_0"; 65*4882a593Smuzhiyun function = "gpio"; 66*4882a593Smuzhiyun nxp,gpio-pin-interrupt = <0>; 67*4882a593Smuzhiyun input-enable; 68*4882a593Smuzhiyun bias-disable; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun}; 72