1*4882a593SmuzhiyunDevice tree binding for NVIDIA Tegra XUSB pad controller 2*4882a593Smuzhiyun======================================================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunNOTE: It turns out that this binding isn't an accurate description of the XUSB 5*4882a593Smuzhiyunpad controller. While the description is good enough for the functional subset 6*4882a593Smuzhiyunrequired for PCIe and SATA, it lacks the flexibility to represent the features 7*4882a593Smuzhiyunneeded for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt. 8*4882a593SmuzhiyunThe binding described in this file is deprecated and should not be used. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunThe Tegra XUSB pad controller manages a set of lanes, each of which can be 11*4882a593Smuzhiyunassigned to one out of a set of different pads. Some of these pads have an 12*4882a593Smuzhiyunassociated PHY that must be powered up before the pad can be used. 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunThis document defines the device-specific binding for the XUSB pad controller. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunRefer to pinctrl-bindings.txt in this directory for generic information about 17*4882a593Smuzhiyunpin controller device tree bindings and ../phy/phy-bindings.txt for details on 18*4882a593Smuzhiyunhow to describe and reference PHYs in device trees. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunRequired properties: 21*4882a593Smuzhiyun-------------------- 22*4882a593Smuzhiyun- compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl". 23*4882a593Smuzhiyun Otherwise, must contain '"nvidia,<chip>-xusb-padctl", 24*4882a593Smuzhiyun "nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210. 25*4882a593Smuzhiyun- reg: Physical base address and length of the controller's registers. 26*4882a593Smuzhiyun- resets: Must contain an entry for each entry in reset-names. 27*4882a593Smuzhiyun See ../reset/reset.txt for details. 28*4882a593Smuzhiyun- reset-names: Must include the following entries: 29*4882a593Smuzhiyun - padctl 30*4882a593Smuzhiyun- #phy-cells: Should be 1. The specifier is the index of the PHY to reference. 31*4882a593Smuzhiyun See <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> for the list of valid values. 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunLane muxing: 34*4882a593Smuzhiyun------------ 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunChild nodes contain the pinmux configurations following the conventions from 37*4882a593Smuzhiyunthe pinctrl-bindings.txt document. Typically a single, static configuration is 38*4882a593Smuzhiyungiven and applied at boot time. 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunEach subnode describes groups of lanes along with parameters and pads that 41*4882a593Smuzhiyunthey should be assigned to. The name of these subnodes is not important. All 42*4882a593Smuzhiyunsubnodes should be parsed solely based on their content. 43*4882a593Smuzhiyun 44*4882a593SmuzhiyunEach subnode only applies the parameters that are explicitly listed. In other 45*4882a593Smuzhiyunwords, if a subnode that lists a function but no pin configuration parameters 46*4882a593Smuzhiyunimplies no information about any pin configuration parameters. Similarly, a 47*4882a593Smuzhiyunsubnode that describes only an IDDQ parameter implies no information about 48*4882a593Smuzhiyunwhat function the pins are assigned to. For this reason even seemingly boolean 49*4882a593Smuzhiyunvalues are actually tristates in this binding: unspecified, off or on. 50*4882a593SmuzhiyunUnspecified is represented as an absent property, and off/on are represented 51*4882a593Smuzhiyunas integer values 0 and 1. 52*4882a593Smuzhiyun 53*4882a593SmuzhiyunRequired properties: 54*4882a593Smuzhiyun- nvidia,lanes: An array of strings. Each string is the name of a lane. 55*4882a593Smuzhiyun 56*4882a593SmuzhiyunOptional properties: 57*4882a593Smuzhiyun- nvidia,function: A string that is the name of the function (pad) that the 58*4882a593Smuzhiyun pin or group should be assigned to. Valid values for function names are 59*4882a593Smuzhiyun listed below. 60*4882a593Smuzhiyun- nvidia,iddq: Enables IDDQ mode of the lane. (0: no, 1: yes) 61*4882a593Smuzhiyun 62*4882a593SmuzhiyunNote that not all of these properties are valid for all lanes. Lanes can be 63*4882a593Smuzhiyundivided into three groups: 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun - otg-0, otg-1, otg-2: 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun Valid functions for this group are: "snps", "xusb", "uart", "rsvd". 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun The nvidia,iddq property does not apply to this group. 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun - ulpi-0, hsic-0, hsic-1: 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun Valid functions for this group are: "snps", "xusb". 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun The nvidia,iddq property does not apply to this group. 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun - pcie-0, pcie-1, pcie-2, pcie-3, pcie-4, sata-0: 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun Valid functions for this group are: "pcie", "usb3", "sata", "rsvd". 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun 82*4882a593SmuzhiyunExample: 83*4882a593Smuzhiyun======== 84*4882a593Smuzhiyun 85*4882a593SmuzhiyunSoC file extract: 86*4882a593Smuzhiyun----------------- 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun padctl@7009f000 { 89*4882a593Smuzhiyun compatible = "nvidia,tegra124-xusb-padctl"; 90*4882a593Smuzhiyun reg = <0x0 0x7009f000 0x0 0x1000>; 91*4882a593Smuzhiyun resets = <&tegra_car 142>; 92*4882a593Smuzhiyun reset-names = "padctl"; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #phy-cells = <1>; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593SmuzhiyunBoard file extract: 98*4882a593Smuzhiyun------------------- 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun pcie-controller@1003000 { 101*4882a593Smuzhiyun ... 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun phys = <&padctl 0>; 104*4882a593Smuzhiyun phy-names = "pcie"; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun ... 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun ... 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun padctl: padctl@7009f000 { 112*4882a593Smuzhiyun pinctrl-0 = <&padctl_default>; 113*4882a593Smuzhiyun pinctrl-names = "default"; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun padctl_default: pinmux { 116*4882a593Smuzhiyun usb3 { 117*4882a593Smuzhiyun nvidia,lanes = "pcie-0", "pcie-1"; 118*4882a593Smuzhiyun nvidia,function = "usb3"; 119*4882a593Smuzhiyun nvidia,iddq = <0>; 120*4882a593Smuzhiyun }; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun pcie { 123*4882a593Smuzhiyun nvidia,lanes = "pcie-2", "pcie-3", 124*4882a593Smuzhiyun "pcie-4"; 125*4882a593Smuzhiyun nvidia,function = "pcie"; 126*4882a593Smuzhiyun nvidia,iddq = <0>; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun sata { 130*4882a593Smuzhiyun nvidia,lanes = "sata-0"; 131*4882a593Smuzhiyun nvidia,function = "sata"; 132*4882a593Smuzhiyun nvidia,iddq = <0>; 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun }; 136