1*4882a593SmuzhiyunDevice tree binding for NVIDIA Tegra DPAUX pad controller 2*4882a593Smuzhiyun======================================================== 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe Tegra Display Port Auxiliary (DPAUX) pad controller manages two pins 5*4882a593Smuzhiyunwhich can be assigned to either the DPAUX channel or to an I2C 6*4882a593Smuzhiyuncontroller. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunThis document defines the device-specific binding for the DPAUX pad 9*4882a593Smuzhiyuncontroller. Refer to pinctrl-bindings.txt in this directory for generic 10*4882a593Smuzhiyuninformation about pin controller device tree bindings. Please refer to 11*4882a593Smuzhiyunthe binding document ../display/tegra/nvidia,tegra20-host1x.txt for more 12*4882a593Smuzhiyundetails on the DPAUX binding. 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunPin muxing: 15*4882a593Smuzhiyun----------- 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunChild nodes contain the pinmux configurations following the conventions 18*4882a593Smuzhiyunfrom the pinctrl-bindings.txt document. 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunSince only three configurations are possible, only three child nodes are 21*4882a593Smuzhiyunneeded to describe the pin mux'ing options for the DPAUX pads. 22*4882a593SmuzhiyunFurthermore, given that the pad functions are only applicable to a 23*4882a593Smuzhiyunsingle set of pads, the child nodes only need to describe the pad group 24*4882a593Smuzhiyunthe functions are being applied to rather than the individual pads. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunRequired properties: 27*4882a593Smuzhiyun- groups: Must be "dpaux-io" 28*4882a593Smuzhiyun- function: Must be either "aux", "i2c" or "off". 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunExample: 31*4882a593Smuzhiyun-------- 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun dpaux@545c0000 { 34*4882a593Smuzhiyun ... 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun state_dpaux_aux: pinmux-aux { 37*4882a593Smuzhiyun groups = "dpaux-io"; 38*4882a593Smuzhiyun function = "aux"; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun state_dpaux_i2c: pinmux-i2c { 42*4882a593Smuzhiyun groups = "dpaux-io"; 43*4882a593Smuzhiyun function = "i2c"; 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun state_dpaux_off: pinmux-off { 47*4882a593Smuzhiyun groups = "dpaux-io"; 48*4882a593Smuzhiyun function = "off"; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun ... 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun i2c@7000d100 { 55*4882a593Smuzhiyun ... 56*4882a593Smuzhiyun pinctrl-0 = <&state_dpaux_i2c>; 57*4882a593Smuzhiyun pinctrl-1 = <&state_dpaux_off>; 58*4882a593Smuzhiyun pinctrl-names = "default", "idle"; 59*4882a593Smuzhiyun }; 60