1*4882a593SmuzhiyunNuvoton NPCM7XX Pin Controllers 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Nuvoton BMC NPCM7XX Pin Controller multi-function routed through 4*4882a593Smuzhiyunthe multiplexing block, Each pin supports GPIO functionality (GPIOx) 5*4882a593Smuzhiyunand multiple functions that directly connect the pin to different 6*4882a593Smuzhiyunhardware blocks. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties: 9*4882a593Smuzhiyun- #address-cells : should be 1. 10*4882a593Smuzhiyun- #size-cells : should be 1. 11*4882a593Smuzhiyun- compatible : "nuvoton,npcm750-pinctrl" for Poleg NPCM7XX. 12*4882a593Smuzhiyun- ranges : defines mapping ranges between pin controller node (parent) 13*4882a593Smuzhiyun to GPIO bank node (children). 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun=== GPIO Bank Subnode === 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunThe NPCM7XX has 8 GPIO Banks each GPIO bank supports 32 GPIO. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunRequired GPIO Bank subnode-properties: 20*4882a593Smuzhiyun- reg : specifies physical base address and size of the GPIO 21*4882a593Smuzhiyun bank registers. 22*4882a593Smuzhiyun- gpio-controller : Marks the device node as a GPIO controller. 23*4882a593Smuzhiyun- #gpio-cells : Must be <2>. The first cell is the gpio pin number 24*4882a593Smuzhiyun and the second cell is used for optional parameters. 25*4882a593Smuzhiyun- interrupts : contain the GPIO bank interrupt with flags for falling edge. 26*4882a593Smuzhiyun- gpio-ranges : defines the range of pins managed by the GPIO bank controller. 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunFor example, GPIO bank subnodes like the following: 29*4882a593Smuzhiyun gpio0: gpio@f0010000 { 30*4882a593Smuzhiyun gpio-controller; 31*4882a593Smuzhiyun #gpio-cells = <2>; 32*4882a593Smuzhiyun reg = <0x0 0x80>; 33*4882a593Smuzhiyun interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 34*4882a593Smuzhiyun gpio-ranges = <&pinctrl 0 0 32>; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun=== Pin Mux Subnode === 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun- pin: A string containing the name of the pin 40*4882a593Smuzhiyun An array of strings, each string containing the name of a pin. 41*4882a593Smuzhiyun These pin are used for selecting pin configuration. 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunThe following are the list of pins available: 44*4882a593Smuzhiyun "GPIO0/IOX1DI", "GPIO1/IOX1LD", "GPIO2/IOX1CK", "GPIO3/IOX1D0", 45*4882a593Smuzhiyun "GPIO4/IOX2DI/SMB1DSDA", "GPIO5/IOX2LD/SMB1DSCL", "GPIO6/IOX2CK/SMB2DSDA", 46*4882a593Smuzhiyun "GPIO7/IOX2D0/SMB2DSCL", "GPIO8/LKGPO1", "GPIO9/LKGPO2", "GPIO10/IOXHLD", 47*4882a593Smuzhiyun "GPIO11/IOXHCK", "GPIO12/GSPICK/SMB5BSCL", "GPIO13/GSPIDO/SMB5BSDA", 48*4882a593Smuzhiyun "GPIO14/GSPIDI/SMB5CSCL", "GPIO15/GSPICS/SMB5CSDA", "GPIO16/LKGPO0", 49*4882a593Smuzhiyun "GPIO17/PSPI2DI/SMB4DEN","GPIO18/PSPI2D0/SMB4BSDA", "GPIO19/PSPI2CK/SMB4BSCL", 50*4882a593Smuzhiyun "GPIO20/SMB4CSDA/SMB15SDA", "GPIO21/SMB4CSCL/SMB15SCL", "GPIO22/SMB4DSDA/SMB14SDA", 51*4882a593Smuzhiyun "GPIO23/SMB4DSCL/SMB14SCL", "GPIO24/IOXHDO", "GPIO25/IOXHDI", "GPIO26/SMB5SDA", 52*4882a593Smuzhiyun "GPIO27/SMB5SCL", "GPIO28/SMB4SDA", "GPIO29/SMB4SCL", "GPIO30/SMB3SDA", 53*4882a593Smuzhiyun "GPIO31/SMB3SCL", "GPIO32/nSPI0CS1","SPI0D2", "SPI0D3", "GPIO37/SMB3CSDA", 54*4882a593Smuzhiyun "GPIO38/SMB3CSCL", "GPIO39/SMB3BSDA", "GPIO40/SMB3BSCL", "GPIO41/BSPRXD", 55*4882a593Smuzhiyun "GPO42/BSPTXD/STRAP11", "GPIO43/RXD1/JTMS2/BU1RXD", "GPIO44/nCTS1/JTDI2/BU1CTS", 56*4882a593Smuzhiyun "GPIO45/nDCD1/JTDO2", "GPIO46/nDSR1/JTCK2", "GPIO47/nRI1/JCP_RDY2", 57*4882a593Smuzhiyun "GPIO48/TXD2/BSPTXD", "GPIO49/RXD2/BSPRXD", "GPIO50/nCTS2", "GPO51/nRTS2/STRAP2", 58*4882a593Smuzhiyun "GPIO52/nDCD2", "GPO53/nDTR2_BOUT2/STRAP1", "GPIO54/nDSR2", "GPIO55/nRI2", 59*4882a593Smuzhiyun "GPIO56/R1RXERR", "GPIO57/R1MDC", "GPIO58/R1MDIO", "GPIO59/SMB3DSDA", 60*4882a593Smuzhiyun "GPIO60/SMB3DSCL", "GPO61/nDTR1_BOUT1/STRAP6", "GPO62/nRTST1/STRAP5", 61*4882a593Smuzhiyun "GPO63/TXD1/STRAP4", "GPIO64/FANIN0", "GPIO65/FANIN1", "GPIO66/FANIN2", 62*4882a593Smuzhiyun "GPIO67/FANIN3", "GPIO68/FANIN4", "GPIO69/FANIN5", "GPIO70/FANIN6", "GPIO71/FANIN7", 63*4882a593Smuzhiyun "GPIO72/FANIN8", "GPIO73/FANIN9", "GPIO74/FANIN10", "GPIO75/FANIN11", 64*4882a593Smuzhiyun "GPIO76/FANIN12", "GPIO77/FANIN13","GPIO78/FANIN14", "GPIO79/FANIN15", 65*4882a593Smuzhiyun "GPIO80/PWM0", "GPIO81/PWM1", "GPIO82/PWM2", "GPIO83/PWM3", "GPIO84/R2TXD0", 66*4882a593Smuzhiyun "GPIO85/R2TXD1", "GPIO86/R2TXEN", "GPIO87/R2RXD0", "GPIO88/R2RXD1", "GPIO89/R2CRSDV", 67*4882a593Smuzhiyun "GPIO90/R2RXERR", "GPIO91/R2MDC", "GPIO92/R2MDIO", "GPIO93/GA20/SMB5DSCL", 68*4882a593Smuzhiyun "GPIO94/nKBRST/SMB5DSDA", "GPIO95/nLRESET/nESPIRST", "GPIO96/RG1TXD0", 69*4882a593Smuzhiyun "GPIO97/RG1TXD1", "GPIO98/RG1TXD2", "GPIO99/RG1TXD3","GPIO100/RG1TXC", 70*4882a593Smuzhiyun "GPIO101/RG1TXCTL", "GPIO102/RG1RXD0", "GPIO103/RG1RXD1", "GPIO104/RG1RXD2", 71*4882a593Smuzhiyun "GPIO105/RG1RXD3", "GPIO106/RG1RXC", "GPIO107/RG1RXCTL", "GPIO108/RG1MDC", 72*4882a593Smuzhiyun "GPIO109/RG1MDIO", "GPIO110/RG2TXD0/DDRV0", "GPIO111/RG2TXD1/DDRV1", 73*4882a593Smuzhiyun "GPIO112/RG2TXD2/DDRV2", "GPIO113/RG2TXD3/DDRV3", "GPIO114/SMB0SCL", 74*4882a593Smuzhiyun "GPIO115/SMB0SDA", "GPIO116/SMB1SCL", "GPIO117/SMB1SDA", "GPIO118/SMB2SCL", 75*4882a593Smuzhiyun "GPIO119/SMB2SDA", "GPIO120/SMB2CSDA", "GPIO121/SMB2CSCL", "GPIO122/SMB2BSDA", 76*4882a593Smuzhiyun "GPIO123/SMB2BSCL", "GPIO124/SMB1CSDA", "GPIO125/SMB1CSCL","GPIO126/SMB1BSDA", 77*4882a593Smuzhiyun "GPIO127/SMB1BSCL", "GPIO128/SMB8SCL", "GPIO129/SMB8SDA", "GPIO130/SMB9SCL", 78*4882a593Smuzhiyun "GPIO131/SMB9SDA", "GPIO132/SMB10SCL", "GPIO133/SMB10SDA","GPIO134/SMB11SCL", 79*4882a593Smuzhiyun "GPIO135/SMB11SDA", "GPIO136/SD1DT0", "GPIO137/SD1DT1", "GPIO138/SD1DT2", 80*4882a593Smuzhiyun "GPIO139/SD1DT3", "GPIO140/SD1CLK", "GPIO141/SD1WP", "GPIO142/SD1CMD", 81*4882a593Smuzhiyun "GPIO143/SD1CD/SD1PWR", "GPIO144/PWM4", "GPIO145/PWM5", "GPIO146/PWM6", 82*4882a593Smuzhiyun "GPIO147/PWM7", "GPIO148/MMCDT4", "GPIO149/MMCDT5", "GPIO150/MMCDT6", 83*4882a593Smuzhiyun "GPIO151/MMCDT7", "GPIO152/MMCCLK", "GPIO153/MMCWP", "GPIO154/MMCCMD", 84*4882a593Smuzhiyun "GPIO155/nMMCCD/nMMCRST", "GPIO156/MMCDT0", "GPIO157/MMCDT1", "GPIO158/MMCDT2", 85*4882a593Smuzhiyun "GPIO159/MMCDT3", "GPIO160/CLKOUT/RNGOSCOUT", "GPIO161/nLFRAME/nESPICS", 86*4882a593Smuzhiyun "GPIO162/SERIRQ", "GPIO163/LCLK/ESPICLK", "GPIO164/LAD0/ESPI_IO0", 87*4882a593Smuzhiyun "GPIO165/LAD1/ESPI_IO1", "GPIO166/LAD2/ESPI_IO2", "GPIO167/LAD3/ESPI_IO3", 88*4882a593Smuzhiyun "GPIO168/nCLKRUN/nESPIALERT", "GPIO169/nSCIPME", "GPIO170/nSMI", "GPIO171/SMB6SCL", 89*4882a593Smuzhiyun "GPIO172/SMB6SDA", "GPIO173/SMB7SCL", "GPIO174/SMB7SDA", "GPIO175/PSPI1CK/FANIN19", 90*4882a593Smuzhiyun "GPIO176/PSPI1DO/FANIN18", "GPIO177/PSPI1DI/FANIN17", "GPIO178/R1TXD0", 91*4882a593Smuzhiyun "GPIO179/R1TXD1", "GPIO180/R1TXEN", "GPIO181/R1RXD0", "GPIO182/R1RXD1", 92*4882a593Smuzhiyun "GPIO183/SPI3CK", "GPO184/SPI3D0/STRAP9", "GPO185/SPI3D1/STRAP10", 93*4882a593Smuzhiyun "GPIO186/nSPI3CS0", "GPIO187/nSPI3CS1", "GPIO188/SPI3D2/nSPI3CS2", 94*4882a593Smuzhiyun "GPIO189/SPI3D3/nSPI3CS3", "GPIO190/nPRD_SMI", "GPIO191", "GPIO192", "GPIO193/R1CRSDV", 95*4882a593Smuzhiyun "GPIO194/SMB0BSCL", "GPIO195/SMB0BSDA", "GPIO196/SMB0CSCL", "GPIO197/SMB0DEN", 96*4882a593Smuzhiyun "GPIO198/SMB0DSDA", "GPIO199/SMB0DSCL", "GPIO200/R2CK", "GPIO201/R1CK", 97*4882a593Smuzhiyun "GPIO202/SMB0CSDA", "GPIO203/FANIN16", "GPIO204/DDC2SCL", "GPIO205/DDC2SDA", 98*4882a593Smuzhiyun "GPIO206/HSYNC2", "GPIO207/VSYNC2", "GPIO208/RG2TXC/DVCK", "GPIO209/RG2TXCTL/DDRV4", 99*4882a593Smuzhiyun "GPIO210/RG2RXD0/DDRV5", "GPIO211/RG2RXD1/DDRV6", "GPIO212/RG2RXD2/DDRV7", 100*4882a593Smuzhiyun "GPIO213/RG2RXD3/DDRV8", "GPIO214/RG2RXC/DDRV9", "GPIO215/RG2RXCTL/DDRV10", 101*4882a593Smuzhiyun "GPIO216/RG2MDC/DDRV11", "GPIO217/RG2MDIO/DVHSYNC", "GPIO218/nWDO1", 102*4882a593Smuzhiyun "GPIO219/nWDO2", "GPIO220/SMB12SCL", "GPIO221/SMB12SDA", "GPIO222/SMB13SCL", 103*4882a593Smuzhiyun "GPIO223/SMB13SDA", "GPIO224/SPIXCK", "GPO225/SPIXD0/STRAP12", "GPO226/SPIXD1/STRAP13", 104*4882a593Smuzhiyun "GPIO227/nSPIXCS0", "GPIO228/nSPIXCS1", "GPO229/SPIXD2/STRAP3", "GPIO230/SPIXD3", 105*4882a593Smuzhiyun "GPIO231/nCLKREQ", "GPI255/DACOSEL" 106*4882a593Smuzhiyun 107*4882a593SmuzhiyunOptional Properties: 108*4882a593Smuzhiyun bias-disable, bias-pull-down, bias-pull-up, input-enable, 109*4882a593Smuzhiyun input-disable, output-high, output-low, drive-push-pull, 110*4882a593Smuzhiyun drive-open-drain, input-debounce, slew-rate, drive-strength 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun slew-rate valid arguments are: 113*4882a593Smuzhiyun <0> - slow 114*4882a593Smuzhiyun <1> - fast 115*4882a593Smuzhiyun drive-strength valid arguments are: 116*4882a593Smuzhiyun <2> - 2mA 117*4882a593Smuzhiyun <4> - 4mA 118*4882a593Smuzhiyun <8> - 8mA 119*4882a593Smuzhiyun <12> - 12mA 120*4882a593Smuzhiyun <16> - 16mA 121*4882a593Smuzhiyun <24> - 24mA 122*4882a593Smuzhiyun 123*4882a593SmuzhiyunFor example, pinctrl might have pinmux subnodes like the following: 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun gpio0_iox1d1_pin: gpio0-iox1d1-pin { 126*4882a593Smuzhiyun pins = "GPIO0/IOX1DI"; 127*4882a593Smuzhiyun output-high; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun gpio0_iox1ck_pin: gpio0-iox1ck-pin { 130*4882a593Smuzhiyun pins = "GPIO2/IOX1CK"; 131*4882a593Smuzhiyun output_high; 132*4882a593Smuzhiyun }; 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun=== Pin Group Subnode === 135*4882a593Smuzhiyun 136*4882a593SmuzhiyunRequired pin group subnode-properties: 137*4882a593Smuzhiyun- groups : A string containing the name of the group to mux. 138*4882a593Smuzhiyun- function: A string containing the name of the function to mux to the 139*4882a593Smuzhiyun group. 140*4882a593Smuzhiyun 141*4882a593SmuzhiyunThe following are the list of the available groups and functions : 142*4882a593Smuzhiyun smb0, smb0b, smb0c, smb0d, smb0den, smb1, smb1b, smb1c, smb1d, 143*4882a593Smuzhiyun smb2, smb2b, smb2c, smb2d, smb3, smb3b, smb3c, smb3d, smb4, smb4b, 144*4882a593Smuzhiyun smb4c, smb4d, smb4den, smb5, smb5b, smb5c, smb5d, ga20kbc, smb6, 145*4882a593Smuzhiyun smb7, smb8, smb9, smb10, smb11, smb12, smb13, smb14, smb15, fanin0, 146*4882a593Smuzhiyun fanin1, fanin2, fanin3, fanin4, fanin5, fanin6, fanin7, fanin8, 147*4882a593Smuzhiyun fanin9, fanin10, fanin11 fanin12 fanin13, fanin14, fanin15, faninx, 148*4882a593Smuzhiyun pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, pwm7, rg1, rg1mdio, rg2, 149*4882a593Smuzhiyun rg2mdio, ddr, uart1, uart2, bmcuart0a, bmcuart0b, bmcuart1, iox1, 150*4882a593Smuzhiyun iox2, ioxh, gspi, mmc, mmcwp, mmccd, mmcrst, mmc8, r1, r1err, r1md, 151*4882a593Smuzhiyun r2, r2err, r2md, sd1, sd1pwr, wdog1, wdog2, scipme, sci, serirq, 152*4882a593Smuzhiyun jtag2, spix, spixcs1, pspi1, pspi2, ddc, clkreq, clkout, spi3, spi3cs1, 153*4882a593Smuzhiyun spi3quad, spi3cs2, spi3cs3, spi0cs1, lpc, lpcclk, espi, lkgpo0, lkgpo1, 154*4882a593Smuzhiyun lkgpo2, nprd_smi 155*4882a593Smuzhiyun 156*4882a593SmuzhiyunFor example, pinctrl might have group subnodes like the following: 157*4882a593Smuzhiyun r1err_pins: r1err-pins { 158*4882a593Smuzhiyun groups = "r1err"; 159*4882a593Smuzhiyun function = "r1err"; 160*4882a593Smuzhiyun }; 161*4882a593Smuzhiyun r1md_pins: r1md-pins { 162*4882a593Smuzhiyun groups = "r1md"; 163*4882a593Smuzhiyun function = "r1md"; 164*4882a593Smuzhiyun }; 165*4882a593Smuzhiyun r1_pins: r1-pins { 166*4882a593Smuzhiyun groups = "r1"; 167*4882a593Smuzhiyun function = "r1"; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun 170*4882a593SmuzhiyunExamples 171*4882a593Smuzhiyun======== 172*4882a593Smuzhiyunpinctrl: pinctrl@f0800000 { 173*4882a593Smuzhiyun #address-cells = <1>; 174*4882a593Smuzhiyun #size-cells = <1>; 175*4882a593Smuzhiyun compatible = "nuvoton,npcm750-pinctrl"; 176*4882a593Smuzhiyun ranges = <0 0xf0010000 0x8000>; 177*4882a593Smuzhiyun 178*4882a593Smuzhiyun gpio0: gpio@f0010000 { 179*4882a593Smuzhiyun gpio-controller; 180*4882a593Smuzhiyun #gpio-cells = <2>; 181*4882a593Smuzhiyun reg = <0x0 0x80>; 182*4882a593Smuzhiyun interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 183*4882a593Smuzhiyun gpio-ranges = <&pinctrl 0 0 32>; 184*4882a593Smuzhiyun }; 185*4882a593Smuzhiyun 186*4882a593Smuzhiyun .... 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun gpio7: gpio@f0017000 { 189*4882a593Smuzhiyun gpio-controller; 190*4882a593Smuzhiyun #gpio-cells = <2>; 191*4882a593Smuzhiyun reg = <0x7000 0x80>; 192*4882a593Smuzhiyun interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 193*4882a593Smuzhiyun gpio-ranges = <&pinctrl 0 224 32>; 194*4882a593Smuzhiyun }; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun gpio0_iox1d1_pin: gpio0-iox1d1-pin { 197*4882a593Smuzhiyun pins = "GPIO0/IOX1DI"; 198*4882a593Smuzhiyun output-high; 199*4882a593Smuzhiyun }; 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun iox1_pins: iox1-pins { 202*4882a593Smuzhiyun groups = "iox1"; 203*4882a593Smuzhiyun function = "iox1"; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun iox2_pins: iox2-pins { 206*4882a593Smuzhiyun groups = "iox2"; 207*4882a593Smuzhiyun function = "iox2"; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun .... 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun clkreq_pins: clkreq-pins { 213*4882a593Smuzhiyun groups = "clkreq"; 214*4882a593Smuzhiyun function = "clkreq"; 215*4882a593Smuzhiyun }; 216*4882a593Smuzhiyun}; 217