1*4882a593SmuzhiyunMicrosemi Ocelot pin controller Device Tree Bindings 2*4882a593Smuzhiyun---------------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun - compatible : Should be "mscc,ocelot-pinctrl", 6*4882a593Smuzhiyun "mscc,jaguar2-pinctrl" or "microchip,sparx5-pinctrl" 7*4882a593Smuzhiyun - reg : Address and length of the register set for the device 8*4882a593Smuzhiyun - gpio-controller : Indicates this device is a GPIO controller 9*4882a593Smuzhiyun - #gpio-cells : Must be 2. 10*4882a593Smuzhiyun The first cell is the pin number and the 11*4882a593Smuzhiyun second cell specifies GPIO flags, as defined in 12*4882a593Smuzhiyun <dt-bindings/gpio/gpio.h>. 13*4882a593Smuzhiyun - gpio-ranges : Range of pins managed by the GPIO controller. 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunThe ocelot-pinctrl driver uses the generic pin multiplexing and generic pin 17*4882a593Smuzhiyunconfiguration documented in pinctrl-bindings.txt. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunThe following generic properties are supported: 20*4882a593Smuzhiyun - function 21*4882a593Smuzhiyun - pins 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunExample: 24*4882a593Smuzhiyun gpio: pinctrl@71070034 { 25*4882a593Smuzhiyun compatible = "mscc,ocelot-pinctrl"; 26*4882a593Smuzhiyun reg = <0x71070034 0x28>; 27*4882a593Smuzhiyun gpio-controller; 28*4882a593Smuzhiyun #gpio-cells = <2>; 29*4882a593Smuzhiyun gpio-ranges = <&gpio 0 0 22>; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun uart_pins: uart-pins { 32*4882a593Smuzhiyun pins = "GPIO_6", "GPIO_7"; 33*4882a593Smuzhiyun function = "uart"; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun uart2_pins: uart2-pins { 37*4882a593Smuzhiyun pins = "GPIO_12", "GPIO_13"; 38*4882a593Smuzhiyun function = "uart2"; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun }; 41