1*4882a593Smuzhiyun* Marvell Orion SoC pinctrl driver for mpp 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunPlease refer to marvell,mvebu-pinctrl.txt in this directory for common binding 4*4882a593Smuzhiyunpart and usage. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible: "marvell,88f5181-pinctrl", 8*4882a593Smuzhiyun "marvell,88f5181l-pinctrl", 9*4882a593Smuzhiyun "marvell,88f5182-pinctrl", 10*4882a593Smuzhiyun "marvell,88f5281-pinctrl" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun- reg: two register areas, the first one describing the first two 13*4882a593Smuzhiyun contiguous MPP registers, and the second one describing the single 14*4882a593Smuzhiyun final MPP register, separated from the previous one. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunAvailable mpp pins/groups and functions: 17*4882a593SmuzhiyunNote: brackets (x) are not part of the mpp name for marvell,function and given 18*4882a593Smuzhiyunonly for more detailed description in this document. 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun* Marvell Orion 88f5181l 21*4882a593Smuzhiyun 22*4882a593Smuzhiyunname pins functions 23*4882a593Smuzhiyun================================================================================ 24*4882a593Smuzhiyunmpp0 0 pcie(rstout), pci(req2), gpio 25*4882a593Smuzhiyunmpp1 1 gpio, pci(gnt2) 26*4882a593Smuzhiyunmpp2 2 gpio, pci(req3), pci-1(pme) 27*4882a593Smuzhiyunmpp3 3 gpio, pci(gnt3) 28*4882a593Smuzhiyunmpp4 4 gpio, pci(req4) 29*4882a593Smuzhiyunmpp5 5 gpio, pci(gnt4) 30*4882a593Smuzhiyunmpp6 6 gpio, pci(req5), pci-1(clk) 31*4882a593Smuzhiyunmpp7 7 gpio, pci(gnt5), pci-1(clk) 32*4882a593Smuzhiyunmpp8 8 gpio, ge(col) 33*4882a593Smuzhiyunmpp9 9 gpio, ge(rxerr) 34*4882a593Smuzhiyunmpp10 10 gpio, ge(crs) 35*4882a593Smuzhiyunmpp11 11 gpio, ge(txerr) 36*4882a593Smuzhiyunmpp12 12 gpio, ge(txd4) 37*4882a593Smuzhiyunmpp13 13 gpio, ge(txd5) 38*4882a593Smuzhiyunmpp14 14 gpio, ge(txd6) 39*4882a593Smuzhiyunmpp15 15 gpio, ge(txd7) 40*4882a593Smuzhiyunmpp16 16 ge(rxd4) 41*4882a593Smuzhiyunmpp17 17 ge(rxd5) 42*4882a593Smuzhiyunmpp18 18 ge(rxd6) 43*4882a593Smuzhiyunmpp19 19 ge(rxd7) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun* Marvell Orion 88f5182 46*4882a593Smuzhiyun 47*4882a593Smuzhiyunname pins functions 48*4882a593Smuzhiyun================================================================================ 49*4882a593Smuzhiyunmpp0 0 pcie(rstout), pci(req2), gpio 50*4882a593Smuzhiyunmpp1 1 gpio, pci(gnt2) 51*4882a593Smuzhiyunmpp2 2 gpio, pci(req3), pci-1(pme) 52*4882a593Smuzhiyunmpp3 3 gpio, pci(gnt3) 53*4882a593Smuzhiyunmpp4 4 gpio, pci(req4), bootnand(re), sata0(prsnt) 54*4882a593Smuzhiyunmpp5 5 gpio, pci(gnt4), bootnand(we), sata1(prsnt) 55*4882a593Smuzhiyunmpp6 6 gpio, pci(req5), nand(re0), sata0(act) 56*4882a593Smuzhiyunmpp7 7 gpio, pci(gnt5), nand(we0), sata1(act) 57*4882a593Smuzhiyunmpp8 8 gpio, ge(col) 58*4882a593Smuzhiyunmpp9 9 gpio, ge(rxerr) 59*4882a593Smuzhiyunmpp10 10 gpio, ge(crs) 60*4882a593Smuzhiyunmpp11 11 gpio, ge(txerr) 61*4882a593Smuzhiyunmpp12 12 gpio, ge(txd4), nand(re1), sata0(ledprsnt) 62*4882a593Smuzhiyunmpp13 13 gpio, ge(txd5), nand(we1), sata1(ledprsnt) 63*4882a593Smuzhiyunmpp14 14 gpio, ge(txd6), nand(re2), sata0(ledact) 64*4882a593Smuzhiyunmpp15 15 gpio, ge(txd7), nand(we2), sata1(ledact) 65*4882a593Smuzhiyunmpp16 16 uart1(rxd), ge(rxd4), gpio 66*4882a593Smuzhiyunmpp17 17 uart1(txd), ge(rxd5), gpio 67*4882a593Smuzhiyunmpp18 18 uart1(cts), ge(rxd6), gpio 68*4882a593Smuzhiyunmpp19 19 uart1(rts), ge(rxd7), gpio 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun* Marvell Orion 88f5281 71*4882a593Smuzhiyun 72*4882a593Smuzhiyunname pins functions 73*4882a593Smuzhiyun================================================================================ 74*4882a593Smuzhiyunmpp0 0 pcie(rstout), pci(req2), gpio 75*4882a593Smuzhiyunmpp1 1 gpio, pci(gnt2) 76*4882a593Smuzhiyunmpp2 2 gpio, pci(req3), pci(pme) 77*4882a593Smuzhiyunmpp3 3 gpio, pci(gnt3) 78*4882a593Smuzhiyunmpp4 4 gpio, pci(req4), bootnand(re) 79*4882a593Smuzhiyunmpp5 5 gpio, pci(gnt4), bootnand(we) 80*4882a593Smuzhiyunmpp6 6 gpio, pci(req5), nand(re0) 81*4882a593Smuzhiyunmpp7 7 gpio, pci(gnt5), nand(we0) 82*4882a593Smuzhiyunmpp8 8 gpio, ge(col) 83*4882a593Smuzhiyunmpp9 9 gpio, ge(rxerr) 84*4882a593Smuzhiyunmpp10 10 gpio, ge(crs) 85*4882a593Smuzhiyunmpp11 11 gpio, ge(txerr) 86*4882a593Smuzhiyunmpp12 12 gpio, ge(txd4), nand(re1) 87*4882a593Smuzhiyunmpp13 13 gpio, ge(txd5), nand(we1) 88*4882a593Smuzhiyunmpp14 14 gpio, ge(txd6), nand(re2) 89*4882a593Smuzhiyunmpp15 15 gpio, ge(txd7), nand(we2) 90*4882a593Smuzhiyunmpp16 16 uart1(rxd), ge(rxd4) 91*4882a593Smuzhiyunmpp17 17 uart1(txd), ge(rxd5) 92*4882a593Smuzhiyunmpp18 18 uart1(cts), ge(rxd6) 93*4882a593Smuzhiyunmpp19 19 uart1(rts), ge(rxd7) 94