1*4882a593Smuzhiyun* Marvell Dove SoC pinctrl driver for mpp 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunPlease refer to marvell,mvebu-pinctrl.txt in this directory for common binding 4*4882a593Smuzhiyunpart and usage. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible: "marvell,dove-pinctrl" 8*4882a593Smuzhiyun- clocks: (optional) phandle of pdma clock 9*4882a593Smuzhiyun- reg: register specifiers of MPP, MPP4, and PMU MPP registers 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunAvailable mpp pins/groups and functions: 12*4882a593SmuzhiyunNote: brackets (x) are not part of the mpp name for marvell,function and given 13*4882a593Smuzhiyunonly for more detailed description in this document. 14*4882a593SmuzhiyunNote: pmu* also allows for Power Management functions listed below 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunname pins functions 17*4882a593Smuzhiyun================================================================================ 18*4882a593Smuzhiyunmpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm), pmu* 19*4882a593Smuzhiyunmpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm), pmu* 20*4882a593Smuzhiyunmpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt), 21*4882a593Smuzhiyun uart1(rts), pmu* 22*4882a593Smuzhiyunmpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act), 23*4882a593Smuzhiyun uart1(cts), lcd-spi(cs1), pmu* 24*4882a593Smuzhiyunmpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu* 25*4882a593Smuzhiyunmpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs), pmu* 26*4882a593Smuzhiyunmpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi), pmu* 27*4882a593Smuzhiyunmpp7 7 gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck), pmu* 28*4882a593Smuzhiyunmpp8 8 gpio, pmu, watchdog(rstout), pmu* 29*4882a593Smuzhiyunmpp9 9 gpio, pmu, pex1(clkreq), pmu* 30*4882a593Smuzhiyunmpp10 10 gpio, pmu, ssp(sclk), pmu* 31*4882a593Smuzhiyunmpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl), 32*4882a593Smuzhiyun sdio1(ledctrl), pex0(clkreq), pmu* 33*4882a593Smuzhiyunmpp12 12 gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), 34*4882a593Smuzhiyun sata(act), pmu* 35*4882a593Smuzhiyunmpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp), 36*4882a593Smuzhiyun ssp(extclk), pmu* 37*4882a593Smuzhiyunmpp14 14 gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd), pmu* 38*4882a593Smuzhiyunmpp15 15 gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm), pmu* 39*4882a593Smuzhiyunmpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1) 40*4882a593Smuzhiyunmpp17 17 gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda), 41*4882a593Smuzhiyun ac97-1(sysclko) 42*4882a593Smuzhiyunmpp18 18 gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm) 43*4882a593Smuzhiyunmpp19 19 gpio, uart3(rxd), sdio0(ledctrl), twsi(sck) 44*4882a593Smuzhiyunmpp20 20 gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso), 45*4882a593Smuzhiyun ac97(sysclko) 46*4882a593Smuzhiyunmpp21 21 gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0), 47*4882a593Smuzhiyun uart1(cts), ssp(sfrm) 48*4882a593Smuzhiyunmpp22 22 gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi), 49*4882a593Smuzhiyun lcd-spi(mosi), uart1(cts), ssp(txd) 50*4882a593Smuzhiyunmpp23 23 gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck), 51*4882a593Smuzhiyun lcd-spi(sck), ssp(sclk) 52*4882a593Smuzhiyunmpp_camera 24-39 gpio, camera 53*4882a593Smuzhiyunmpp_sdio0 40-45 gpio, sdio0 54*4882a593Smuzhiyunmpp_sdio1 46-51 gpio, sdio1 55*4882a593Smuzhiyunmpp_audio1 52-57 gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp, 56*4882a593Smuzhiyun ssp/twsi 57*4882a593Smuzhiyunmpp_spi0 58-61 gpio, spi0 58*4882a593Smuzhiyunmpp_uart1 62-63 gpio, uart1 59*4882a593Smuzhiyunmpp_nand 64-71 gpo, nand 60*4882a593Smuzhiyunaudio0 - i2s, ac97 61*4882a593Smuzhiyuntwsi - none, opt1, opt2, opt3 62*4882a593Smuzhiyun 63*4882a593SmuzhiyunPower Management functions (pmu*): 64*4882a593Smuzhiyunpmu-nc Pin not driven by any PM function 65*4882a593Smuzhiyunpmu-low Pin driven low (0) 66*4882a593Smuzhiyunpmu-high Pin driven high (1) 67*4882a593Smuzhiyunpmic(sdi) Pin is used for PMIC SDI 68*4882a593Smuzhiyuncpu-pwr-down Pin is used for CPU_PWRDWN 69*4882a593Smuzhiyunstandby-pwr-down Pin is used for STBY_PWRDWN 70*4882a593Smuzhiyuncore-pwr-good Pin is used for CORE_PWR_GOOD (Pins 0-7 only) 71*4882a593Smuzhiyuncpu-pwr-good Pin is used for CPU_PWR_GOOD (Pins 8-15 only) 72*4882a593Smuzhiyunbat-fault Pin is used for BATTERY_FAULT 73*4882a593Smuzhiyunext0-wakeup Pin is used for EXT0_WU 74*4882a593Smuzhiyunext1-wakeup Pin is used for EXT0_WU 75*4882a593Smuzhiyunext2-wakeup Pin is used for EXT0_WU 76*4882a593Smuzhiyunpmu-blink Pin is used for blink function 77*4882a593Smuzhiyun 78*4882a593SmuzhiyunNotes: 79*4882a593Smuzhiyun* group "mpp_audio1" allows the following functions and gpio pins: 80*4882a593Smuzhiyun - gpio : gpio on pins 52-57 81*4882a593Smuzhiyun - i2s1/spdifo : audio1 i2s on pins 52-55 and spdifo on 57, no gpios 82*4882a593Smuzhiyun - i2s1 : audio1 i2s on pins 52-55, gpio on pins 56,57 83*4882a593Smuzhiyun - spdifo : spdifo on pin 57, gpio on pins 52-55 84*4882a593Smuzhiyun - twsi : twsi on pins 56,57, gpio on pins 52-55 85*4882a593Smuzhiyun - ssp/spdifo : ssp on pins 52-55, spdifo on pin 57, no gpios 86*4882a593Smuzhiyun - ssp : ssp on pins 52-55, gpio on pins 56,57 87*4882a593Smuzhiyun - ssp/twsi : ssp on pins 52-55, twsi on pins 56,57, no gpios 88*4882a593Smuzhiyun* group "audio0" internally muxes i2s0 or ac97 controller to the dedicated 89*4882a593Smuzhiyun audio0 pins. 90*4882a593Smuzhiyun* group "twsi" internally muxes twsi controller to the dedicated or option pins. 91