1*4882a593Smuzhiyun* Marvell Armada XP SoC pinctrl driver for mpp 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunPlease refer to marvell,mvebu-pinctrl.txt in this directory for common binding 4*4882a593Smuzhiyunpart and usage. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl", 8*4882a593Smuzhiyun "marvell,mv78460-pinctrl" 9*4882a593Smuzhiyun- reg: register specifier of MPP registers 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunThis driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunAvailable mpp pins/groups and functions: 14*4882a593SmuzhiyunNote: brackets (x) are not part of the mpp name for marvell,function and given 15*4882a593Smuzhiyunonly for more detailed description in this document. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun* Marvell Armada XP (all variants) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyunname pins functions 20*4882a593Smuzhiyun================================================================================ 21*4882a593Smuzhiyunmpp0 0 gpio, ge0(txclkout), lcd(d0) 22*4882a593Smuzhiyunmpp1 1 gpio, ge0(txd0), lcd(d1) 23*4882a593Smuzhiyunmpp2 2 gpio, ge0(txd1), lcd(d2) 24*4882a593Smuzhiyunmpp3 3 gpio, ge0(txd2), lcd(d3) 25*4882a593Smuzhiyunmpp4 4 gpio, ge0(txd3), lcd(d4) 26*4882a593Smuzhiyunmpp5 5 gpio, ge0(txctl), lcd(d5) 27*4882a593Smuzhiyunmpp6 6 gpio, ge0(rxd0), lcd(d6) 28*4882a593Smuzhiyunmpp7 7 gpio, ge0(rxd1), lcd(d7) 29*4882a593Smuzhiyunmpp8 8 gpio, ge0(rxd2), lcd(d8) 30*4882a593Smuzhiyunmpp9 9 gpio, ge0(rxd3), lcd(d9) 31*4882a593Smuzhiyunmpp10 10 gpio, ge0(rxctl), lcd(d10) 32*4882a593Smuzhiyunmpp11 11 gpio, ge0(rxclk), lcd(d11) 33*4882a593Smuzhiyunmpp12 12 gpio, ge0(txd4), ge1(txclkout), lcd(d12) 34*4882a593Smuzhiyunmpp13 13 gpio, ge0(txd5), ge1(txd0), spi1(mosi), lcd(d13) 35*4882a593Smuzhiyunmpp14 14 gpio, ge0(txd6), ge1(txd1), spi1(sck), lcd(d15) 36*4882a593Smuzhiyunmpp15 15 gpio, ge0(txd7), ge1(txd2), lcd(d16) 37*4882a593Smuzhiyunmpp16 16 gpio, ge0(txd7), ge1(txd3), spi1(cs0), lcd(d16) 38*4882a593Smuzhiyunmpp17 17 gpio, ge0(col), ge1(txctl), spi1(miso), lcd(d17) 39*4882a593Smuzhiyunmpp18 18 gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig) 40*4882a593Smuzhiyunmpp19 19 gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq) 41*4882a593Smuzhiyunmpp20 20 gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk) 42*4882a593Smuzhiyunmpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), dram(bat) 43*4882a593Smuzhiyunmpp22 22 gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt) 44*4882a593Smuzhiyunmpp23 23 gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt) 45*4882a593Smuzhiyunmpp24 24 gpio, lcd(hsync), sata1(prsnt), tdm(rst) 46*4882a593Smuzhiyunmpp25 25 gpio, lcd(vsync), sata0(prsnt), tdm(pclk) 47*4882a593Smuzhiyunmpp26 26 gpio, lcd(clk), tdm(fsync) 48*4882a593Smuzhiyunmpp27 27 gpio, lcd(e), tdm(dtx), ptp(trig) 49*4882a593Smuzhiyunmpp28 28 gpio, lcd(pwm), tdm(drx), ptp(evreq) 50*4882a593Smuzhiyunmpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk) 51*4882a593Smuzhiyunmpp30 30 gpio, tdm(int1), sd0(clk) 52*4882a593Smuzhiyunmpp31 31 gpio, tdm(int2), sd0(cmd) 53*4882a593Smuzhiyunmpp32 32 gpio, tdm(int3), sd0(d0) 54*4882a593Smuzhiyunmpp33 33 gpio, tdm(int4), sd0(d1), dram(bat), dram(vttctrl) 55*4882a593Smuzhiyunmpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt), dram(deccerr) 56*4882a593Smuzhiyunmpp35 35 gpio, tdm(int6), sd0(d3), sata1(prsnt) 57*4882a593Smuzhiyunmpp36 36 gpio, spi0(mosi) 58*4882a593Smuzhiyunmpp37 37 gpio, spi0(miso) 59*4882a593Smuzhiyunmpp38 38 gpio, spi0(sck) 60*4882a593Smuzhiyunmpp39 39 gpio, spi0(cs0) 61*4882a593Smuzhiyunmpp40 40 gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0), 62*4882a593Smuzhiyun spi1(cs1) 63*4882a593Smuzhiyunmpp41 41 gpio, spi0(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt), 64*4882a593Smuzhiyun pcie(clkreq1), spi1(cs2) 65*4882a593Smuzhiyunmpp42 42 gpio, uart2(rxd), uart0(cts), tdm(int7), tdm(timer) 66*4882a593Smuzhiyunmpp43 43 gpio, uart2(txd), uart0(rts), spi0(cs3), pcie(rstout), 67*4882a593Smuzhiyun spi1(cs3) 68*4882a593Smuzhiyunmpp44 44 gpio, uart2(cts), uart3(rxd), spi0(cs4), pcie(clkreq2), 69*4882a593Smuzhiyun dram(bat), spi1(cs4) 70*4882a593Smuzhiyunmpp45 45 gpio, uart2(rts), uart3(txd), spi0(cs5), sata1(prsnt), 71*4882a593Smuzhiyun spi1(cs5), dram(vttctrl) 72*4882a593Smuzhiyunmpp46 46 gpio, uart3(rts), uart1(rts), spi0(cs6), sata0(prsnt), 73*4882a593Smuzhiyun spi1(cs6) 74*4882a593Smuzhiyunmpp47 47 gpio, uart3(cts), uart1(cts), spi0(cs7), pcie(clkreq3), 75*4882a593Smuzhiyun ref(clkout), spi1(cs7) 76*4882a593Smuzhiyunmpp48 48 gpio, dev(clkout), dev(burst/last), nand(rb) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun* Marvell Armada XP (mv78260 and mv78460 only) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyunname pins functions 81*4882a593Smuzhiyun================================================================================ 82*4882a593Smuzhiyunmpp49 49 gpio, dev(we3) 83*4882a593Smuzhiyunmpp50 50 gpio, dev(we2) 84*4882a593Smuzhiyunmpp51 51 gpio, dev(ad16) 85*4882a593Smuzhiyunmpp52 52 gpio, dev(ad17) 86*4882a593Smuzhiyunmpp53 53 gpio, dev(ad18) 87*4882a593Smuzhiyunmpp54 54 gpio, dev(ad19) 88*4882a593Smuzhiyunmpp55 55 gpio, dev(ad20) 89*4882a593Smuzhiyunmpp56 56 gpio, dev(ad21) 90*4882a593Smuzhiyunmpp57 57 gpio, dev(ad22) 91*4882a593Smuzhiyunmpp58 58 gpio, dev(ad23) 92*4882a593Smuzhiyunmpp59 59 gpio, dev(ad24) 93*4882a593Smuzhiyunmpp60 60 gpio, dev(ad25) 94*4882a593Smuzhiyunmpp61 61 gpio, dev(ad26) 95*4882a593Smuzhiyunmpp62 62 gpio, dev(ad27) 96*4882a593Smuzhiyunmpp63 63 gpio, dev(ad28) 97*4882a593Smuzhiyunmpp64 64 gpio, dev(ad29) 98*4882a593Smuzhiyunmpp65 65 gpio, dev(ad30) 99*4882a593Smuzhiyunmpp66 66 gpio, dev(ad31) 100