1*4882a593Smuzhiyun* Marvell 98dx3236 pinctrl driver for mpp
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunPlease refer to marvell,mvebu-pinctrl.txt in this directory for common binding
4*4882a593Smuzhiyunpart and usage
5*4882a593Smuzhiyun
6*4882a593SmuzhiyunRequired properties:
7*4882a593Smuzhiyun- compatible: "marvell,98dx3236-pinctrl" or "marvell,98dx4251-pinctrl"
8*4882a593Smuzhiyun- reg: register specifier of MPP registers
9*4882a593Smuzhiyun
10*4882a593SmuzhiyunThis driver supports all 98dx3236, 98dx3336 and 98dx4251 variants
11*4882a593Smuzhiyun
12*4882a593Smuzhiyunname          pins     functions
13*4882a593Smuzhiyun================================================================================
14*4882a593Smuzhiyunmpp0          0        gpo, spi0(mosi), dev(ad8)
15*4882a593Smuzhiyunmpp1          1        gpio, spi0(miso), dev(ad9)
16*4882a593Smuzhiyunmpp2          2        gpo, spi0(sck), dev(ad10)
17*4882a593Smuzhiyunmpp3          3        gpio, spi0(cs0), dev(ad11)
18*4882a593Smuzhiyunmpp4          4        gpio, spi0(cs1), smi(mdc), dev(cs0)
19*4882a593Smuzhiyunmpp5          5        gpio, pex(rsto), sd0(cmd), dev(bootcs)
20*4882a593Smuzhiyunmpp6          6        gpo, sd0(clk), dev(a2)
21*4882a593Smuzhiyunmpp7          7        gpio, sd0(d0), dev(ale0)
22*4882a593Smuzhiyunmpp8          8        gpio, sd0(d1), dev(ale1)
23*4882a593Smuzhiyunmpp9          9        gpio, sd0(d2), dev(ready0)
24*4882a593Smuzhiyunmpp10         10       gpio, sd0(d3), dev(ad12)
25*4882a593Smuzhiyunmpp11         11       gpio, uart1(rxd), uart0(cts), dev(ad13)
26*4882a593Smuzhiyunmpp12         12       gpo, uart1(txd), uart0(rts), dev(ad14)
27*4882a593Smuzhiyunmpp13         13       gpio, intr(out), dev(ad15)
28*4882a593Smuzhiyunmpp14         14       gpio, i2c0(sck)
29*4882a593Smuzhiyunmpp15         15       gpio, i2c0(sda)
30*4882a593Smuzhiyunmpp16         16       gpo, dev(oe)
31*4882a593Smuzhiyunmpp17         17       gpo, dev(clkout)
32*4882a593Smuzhiyunmpp18         18       gpio, uart1(txd)
33*4882a593Smuzhiyunmpp19         19       gpio, uart1(rxd), dev(rb)
34*4882a593Smuzhiyunmpp20         20       gpo, dev(we0)
35*4882a593Smuzhiyunmpp21         21       gpo, dev(ad0)
36*4882a593Smuzhiyunmpp22         22       gpo, dev(ad1)
37*4882a593Smuzhiyunmpp23         23       gpo, dev(ad2)
38*4882a593Smuzhiyunmpp24         24       gpo, dev(ad3)
39*4882a593Smuzhiyunmpp25         25       gpo, dev(ad4)
40*4882a593Smuzhiyunmpp26         26       gpo, dev(ad5)
41*4882a593Smuzhiyunmpp27         27       gpo, dev(ad6)
42*4882a593Smuzhiyunmpp28         28       gpo, dev(ad7)
43*4882a593Smuzhiyunmpp29         29       gpo, dev(a0)
44*4882a593Smuzhiyunmpp30         30       gpo, dev(a1)
45*4882a593Smuzhiyunmpp31         31       gpio, slv_smi(mdc), smi(mdc), dev(we1)
46*4882a593Smuzhiyunmpp32         32       gpio, slv_smi(mdio), smi(mdio), dev(cs1)
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