1*4882a593Smuzhiyun* Marvell Armada 37xx SoC pin and gpio controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunEach Armada 37xx SoC come with two pin and gpio controller one for the 4*4882a593Smuzhiyunsouth bridge and the other for the north bridge. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunInside this set of register the gpio latch allows exposing some 7*4882a593Smuzhiyunconfiguration of the SoC and especially the clock frequency of the 8*4882a593Smuzhiyunxtal. Hence, this node is a represent as syscon allowing sharing the 9*4882a593Smuzhiyunregister between multiple hardware block. 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunGPIO and pin controller: 12*4882a593Smuzhiyun------------------------ 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunMain node: 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunRefer to pinctrl-bindings.txt in this directory for details of the 17*4882a593Smuzhiyuncommon pinctrl bindings used by client devices, including the meaning 18*4882a593Smuzhiyunof the phrase "pin configuration node". 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunRequired properties for pinctrl driver: 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun- compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd" 23*4882a593Smuzhiyun for the south bridge 24*4882a593Smuzhiyun "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd" 25*4882a593Smuzhiyun for the north bridge 26*4882a593Smuzhiyun- reg: The first set of register are for pinctrl/gpio and the second 27*4882a593Smuzhiyun set for the interrupt controller 28*4882a593Smuzhiyun- interrupts: list of the interrupt use by the gpio 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunAvailable groups and functions for the North bridge: 31*4882a593Smuzhiyun 32*4882a593Smuzhiyungroup: jtag 33*4882a593Smuzhiyun - pins 20-24 34*4882a593Smuzhiyun - functions jtag, gpio 35*4882a593Smuzhiyun 36*4882a593Smuzhiyungroup sdio0 37*4882a593Smuzhiyun - pins 8-10 38*4882a593Smuzhiyun - functions sdio, gpio 39*4882a593Smuzhiyun 40*4882a593Smuzhiyungroup emmc_nb 41*4882a593Smuzhiyun - pins 27-35 42*4882a593Smuzhiyun - functions emmc, gpio 43*4882a593Smuzhiyun 44*4882a593Smuzhiyungroup pwm0 45*4882a593Smuzhiyun - pin 11 (GPIO1-11) 46*4882a593Smuzhiyun - functions pwm, led, gpio 47*4882a593Smuzhiyun 48*4882a593Smuzhiyungroup pwm1 49*4882a593Smuzhiyun - pin 12 50*4882a593Smuzhiyun - functions pwm, led, gpio 51*4882a593Smuzhiyun 52*4882a593Smuzhiyungroup pwm2 53*4882a593Smuzhiyun - pin 13 54*4882a593Smuzhiyun - functions pwm, led, gpio 55*4882a593Smuzhiyun 56*4882a593Smuzhiyungroup pwm3 57*4882a593Smuzhiyun - pin 14 58*4882a593Smuzhiyun - functions pwm, led, gpio 59*4882a593Smuzhiyun 60*4882a593Smuzhiyungroup pmic1 61*4882a593Smuzhiyun - pin 7 62*4882a593Smuzhiyun - functions pmic, gpio 63*4882a593Smuzhiyun 64*4882a593Smuzhiyungroup pmic0 65*4882a593Smuzhiyun - pin 6 66*4882a593Smuzhiyun - functions pmic, gpio 67*4882a593Smuzhiyun 68*4882a593Smuzhiyungroup i2c2 69*4882a593Smuzhiyun - pins 2-3 70*4882a593Smuzhiyun - functions i2c, gpio 71*4882a593Smuzhiyun 72*4882a593Smuzhiyungroup i2c1 73*4882a593Smuzhiyun - pins 0-1 74*4882a593Smuzhiyun - functions i2c, gpio 75*4882a593Smuzhiyun 76*4882a593Smuzhiyungroup spi_cs1 77*4882a593Smuzhiyun - pin 17 78*4882a593Smuzhiyun - functions spi, gpio 79*4882a593Smuzhiyun 80*4882a593Smuzhiyungroup spi_cs2 81*4882a593Smuzhiyun - pin 18 82*4882a593Smuzhiyun - functions spi, gpio 83*4882a593Smuzhiyun 84*4882a593Smuzhiyungroup spi_cs3 85*4882a593Smuzhiyun - pin 19 86*4882a593Smuzhiyun - functions spi, gpio 87*4882a593Smuzhiyun 88*4882a593Smuzhiyungroup onewire 89*4882a593Smuzhiyun - pin 4 90*4882a593Smuzhiyun - functions onewire, gpio 91*4882a593Smuzhiyun 92*4882a593Smuzhiyungroup uart1 93*4882a593Smuzhiyun - pins 25-26 94*4882a593Smuzhiyun - functions uart, gpio 95*4882a593Smuzhiyun 96*4882a593Smuzhiyungroup spi_quad 97*4882a593Smuzhiyun - pins 15-16 98*4882a593Smuzhiyun - functions spi, gpio 99*4882a593Smuzhiyun 100*4882a593Smuzhiyungroup uart2 101*4882a593Smuzhiyun - pins 9-10 and 18-19 102*4882a593Smuzhiyun - functions uart, gpio 103*4882a593Smuzhiyun 104*4882a593SmuzhiyunAvailable groups and functions for the South bridge: 105*4882a593Smuzhiyun 106*4882a593Smuzhiyungroup usb32_drvvbus0 107*4882a593Smuzhiyun - pin 36 108*4882a593Smuzhiyun - functions drvbus, gpio 109*4882a593Smuzhiyun 110*4882a593Smuzhiyungroup usb2_drvvbus1 111*4882a593Smuzhiyun - pin 37 112*4882a593Smuzhiyun - functions drvbus, gpio 113*4882a593Smuzhiyun 114*4882a593Smuzhiyungroup sdio_sb 115*4882a593Smuzhiyun - pins 60-65 116*4882a593Smuzhiyun - functions sdio, gpio 117*4882a593Smuzhiyun 118*4882a593Smuzhiyungroup rgmii 119*4882a593Smuzhiyun - pins 42-53 120*4882a593Smuzhiyun - functions mii, gpio 121*4882a593Smuzhiyun 122*4882a593Smuzhiyungroup pcie1 123*4882a593Smuzhiyun - pins 39 124*4882a593Smuzhiyun - functions pcie, gpio 125*4882a593Smuzhiyun 126*4882a593Smuzhiyungroup pcie1_clkreq 127*4882a593Smuzhiyun - pins 40 128*4882a593Smuzhiyun - functions pcie, gpio 129*4882a593Smuzhiyun 130*4882a593Smuzhiyungroup pcie1_wakeup 131*4882a593Smuzhiyun - pins 41 132*4882a593Smuzhiyun - functions pcie, gpio 133*4882a593Smuzhiyun 134*4882a593Smuzhiyungroup smi 135*4882a593Smuzhiyun - pins 54-55 136*4882a593Smuzhiyun - functions smi, gpio 137*4882a593Smuzhiyun 138*4882a593Smuzhiyungroup ptp 139*4882a593Smuzhiyun - pins 56 140*4882a593Smuzhiyun - functions ptp, gpio 141*4882a593Smuzhiyun 142*4882a593Smuzhiyungroup ptp_clk 143*4882a593Smuzhiyun - pin 57 144*4882a593Smuzhiyun - functions ptp, mii 145*4882a593Smuzhiyun 146*4882a593Smuzhiyungroup ptp_trig 147*4882a593Smuzhiyun - pin 58 148*4882a593Smuzhiyun - functions ptp, mii 149*4882a593Smuzhiyun 150*4882a593Smuzhiyungroup mii_col 151*4882a593Smuzhiyun - pin 59 152*4882a593Smuzhiyun - functions mii, mii_err 153*4882a593Smuzhiyun 154*4882a593SmuzhiyunGPIO subnode: 155*4882a593Smuzhiyun 156*4882a593SmuzhiyunPlease refer to gpio.txt in this directory for details of gpio-ranges property 157*4882a593Smuzhiyunand the common GPIO bindings used by client devices. 158*4882a593Smuzhiyun 159*4882a593SmuzhiyunRequired properties for gpio driver under the gpio subnode: 160*4882a593Smuzhiyun- interrupts: List of interrupt specifier for the controllers interrupt. 161*4882a593Smuzhiyun- gpio-controller: Marks the device node as a gpio controller. 162*4882a593Smuzhiyun- #gpio-cells: Should be 2. The first cell is the GPIO number and the 163*4882a593Smuzhiyun second cell specifies GPIO flags, as defined in 164*4882a593Smuzhiyun <dt-bindings/gpio/gpio.h>. Only the GPIO_ACTIVE_HIGH and 165*4882a593Smuzhiyun GPIO_ACTIVE_LOW flags are supported. 166*4882a593Smuzhiyun- gpio-ranges: Range of pins managed by the GPIO controller. 167*4882a593Smuzhiyun 168*4882a593SmuzhiyunXtal Clock bindings for Marvell Armada 37xx SoCs 169*4882a593Smuzhiyun------------------------------------------------ 170*4882a593Smuzhiyun 171*4882a593Smuzhiyunsee Documentation/devicetree/bindings/clock/armada3700-xtal-clock.txt 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun 174*4882a593SmuzhiyunExample: 175*4882a593Smuzhiyunpinctrl_sb: pinctrl-sb@18800 { 176*4882a593Smuzhiyun compatible = "marvell,armada3710-sb-pinctrl", "syscon", "simple-mfd"; 177*4882a593Smuzhiyun reg = <0x18800 0x100>, <0x18C00 0x20>; 178*4882a593Smuzhiyun gpio { 179*4882a593Smuzhiyun #gpio-cells = <2>; 180*4882a593Smuzhiyun gpio-ranges = <&pinctrl_sb 0 0 29>; 181*4882a593Smuzhiyun gpio-controller; 182*4882a593Smuzhiyun interrupts = 183*4882a593Smuzhiyun <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 184*4882a593Smuzhiyun <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 185*4882a593Smuzhiyun <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 186*4882a593Smuzhiyun <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 187*4882a593Smuzhiyun <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun rgmii_pins: mii-pins { 191*4882a593Smuzhiyun groups = "rgmii"; 192*4882a593Smuzhiyun function = "mii"; 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun}; 196