1*4882a593Smuzhiyun* Marvell Armada 375 SoC pinctrl driver for mpp 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunPlease refer to marvell,mvebu-pinctrl.txt in this directory for common binding 4*4882a593Smuzhiyunpart and usage. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible: "marvell,88f6720-pinctrl" 8*4882a593Smuzhiyun- reg: register specifier of MPP registers 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunAvailable mpp pins/groups and functions: 11*4882a593SmuzhiyunNote: brackets (x) are not part of the mpp name for marvell,function and given 12*4882a593Smuzhiyunonly for more detailed description in this document. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyunname pins functions 15*4882a593Smuzhiyun================================================================================ 16*4882a593Smuzhiyunmpp0 0 gpio, dev(ad2), spi0(cs1), spi1(cs1) 17*4882a593Smuzhiyunmpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi) 18*4882a593Smuzhiyunmpp2 2 gpio, dev(ad4), ptp(evreq), led(c0), audio(sdi) 19*4882a593Smuzhiyunmpp3 3 gpio, dev(ad5), ptp(trig), led(p3), audio(mclk) 20*4882a593Smuzhiyunmpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso) 21*4882a593Smuzhiyunmpp5 5 gpio, dev(ad7), spi0(cs2), spi1(cs2) 22*4882a593Smuzhiyunmpp6 6 gpio, dev(ad0), led(p1), audio(lrclk) 23*4882a593Smuzhiyunmpp7 7 gpio, dev(ad1), ptp(clk), led(p2), audio(extclk) 24*4882a593Smuzhiyunmpp8 8 gpio, dev (bootcs), spi0(cs0), spi1(cs0) 25*4882a593Smuzhiyunmpp9 9 gpio, spi0(sck), spi1(sck), nand(we) 26*4882a593Smuzhiyunmpp10 10 gpio, dram(vttctrl), led(c1), nand(re) 27*4882a593Smuzhiyunmpp11 11 gpio, dev(a0), led(c2), audio(sdo) 28*4882a593Smuzhiyunmpp12 12 gpio, dev(a1), audio(bclk) 29*4882a593Smuzhiyunmpp13 13 gpio, dev(ready), pcie0(rstout), pcie1(rstout) 30*4882a593Smuzhiyunmpp14 14 gpio, i2c0(sda), uart1(txd) 31*4882a593Smuzhiyunmpp15 15 gpio, i2c0(sck), uart1(rxd) 32*4882a593Smuzhiyunmpp16 16 gpio, uart0(txd) 33*4882a593Smuzhiyunmpp17 17 gpio, uart0(rxd) 34*4882a593Smuzhiyunmpp18 18 gpio, tdm(int) 35*4882a593Smuzhiyunmpp19 19 gpio, tdm(rst) 36*4882a593Smuzhiyunmpp20 20 gpio, tdm(pclk) 37*4882a593Smuzhiyunmpp21 21 gpio, tdm(fsync) 38*4882a593Smuzhiyunmpp22 22 gpio, tdm(drx) 39*4882a593Smuzhiyunmpp23 23 gpio, tdm(dtx) 40*4882a593Smuzhiyunmpp24 24 gpio, led(p0), ge1(rxd0), sd(cmd), uart0(rts) 41*4882a593Smuzhiyunmpp25 25 gpio, led(p2), ge1(rxd1), sd(d0), uart0(cts) 42*4882a593Smuzhiyunmpp26 26 gpio, pcie0(clkreq), ge1(rxd2), sd(d2), uart1(rts) 43*4882a593Smuzhiyunmpp27 27 gpio, pcie1(clkreq), ge1(rxd3), sd(d1), uart1(cts) 44*4882a593Smuzhiyunmpp28 28 gpio, led(p3), ge1(txctl), sd(clk) 45*4882a593Smuzhiyunmpp29 29 gpio, pcie1(clkreq), ge1(rxclk), sd(d3) 46*4882a593Smuzhiyunmpp30 30 gpio, ge1(txd0), spi1(cs0) 47*4882a593Smuzhiyunmpp31 31 gpio, ge1(txd1), spi1(mosi) 48*4882a593Smuzhiyunmpp32 32 gpio, ge1(txd2), spi1(sck), ptp(trig) 49*4882a593Smuzhiyunmpp33 33 gpio, ge1(txd3), spi1(miso) 50*4882a593Smuzhiyunmpp34 34 gpio, ge1(txclkout), spi1(sck) 51*4882a593Smuzhiyunmpp35 35 gpio, ge1(rxctl), spi1(cs1), spi0(cs2) 52*4882a593Smuzhiyunmpp36 36 gpio, pcie0(clkreq) 53*4882a593Smuzhiyunmpp37 37 gpio, pcie0(clkreq), tdm(int), ge(mdc) 54*4882a593Smuzhiyunmpp38 38 gpio, pcie1(clkreq), ge(mdio) 55*4882a593Smuzhiyunmpp39 39 gpio, ref(clkout) 56*4882a593Smuzhiyunmpp40 40 gpio, uart1(txd) 57*4882a593Smuzhiyunmpp41 41 gpio, uart1(rxd) 58*4882a593Smuzhiyunmpp42 42 gpio, spi1(cs2), led(c0) 59*4882a593Smuzhiyunmpp43 43 gpio, sata0(prsnt), dram(vttctrl) 60*4882a593Smuzhiyunmpp44 44 gpio, sata0(prsnt) 61*4882a593Smuzhiyunmpp45 45 gpio, spi0(cs2), pcie0(rstout) 62*4882a593Smuzhiyunmpp46 46 gpio, led(p0), ge0(txd0), ge1(txd0), dev(we1) 63*4882a593Smuzhiyunmpp47 47 gpio, led(p1), ge0(txd1), ge1(txd1) 64*4882a593Smuzhiyunmpp48 48 gpio, led(p2), ge0(txd2), ge1(txd2) 65*4882a593Smuzhiyunmpp49 49 gpio, led(p3), ge0(txd3), ge1(txd3) 66*4882a593Smuzhiyunmpp50 50 gpio, led(c0), ge0(rxd0), ge1(rxd0) 67*4882a593Smuzhiyunmpp51 51 gpio, led(c1), ge0(rxd1), ge1(rxd1) 68*4882a593Smuzhiyunmpp52 52 gpio, led(c2), ge0(rxd2), ge1(rxd2) 69*4882a593Smuzhiyunmpp53 53 gpio, pcie1(rstout), ge0(rxd3), ge1(rxd3) 70*4882a593Smuzhiyunmpp54 54 gpio, pcie0(rstout), ge0(rxctl), ge1(rxctl) 71*4882a593Smuzhiyunmpp55 55 gpio, ge0(rxclk), ge1(rxclk) 72*4882a593Smuzhiyunmpp56 56 gpio, ge0(txclkout), ge1(txclkout) 73*4882a593Smuzhiyunmpp57 57 gpio, ge0(txctl), ge1(txctl), dev(we0) 74*4882a593Smuzhiyunmpp58 58 gpio, led(c0) 75*4882a593Smuzhiyunmpp59 59 gpio, led(c1) 76*4882a593Smuzhiyunmpp60 60 gpio, uart1(txd), led(c2) 77*4882a593Smuzhiyunmpp61 61 gpio, i2c1(sda), uart1(rxd), spi1(cs2), led(p0) 78*4882a593Smuzhiyunmpp62 62 gpio, i2c1(sck), led(p1) 79*4882a593Smuzhiyunmpp63 63 gpio, ptp(trig), led(p2), dev(burst/last) 80*4882a593Smuzhiyunmpp64 64 gpio, dram(vttctrl), led(p3) 81*4882a593Smuzhiyunmpp65 65 gpio, sata1(prsnt) 82*4882a593Smuzhiyunmpp66 66 gpio, ptp(evreq), spi1(cs3) 83