1*4882a593SmuzhiyunLantiq XWAY pinmux controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: "lantiq,pinctrl-xway", (DEPRECATED: Use "lantiq,pinctrl-danube") 5*4882a593Smuzhiyun "lantiq,pinctrl-xr9", (DEPRECATED: Use "lantiq,xrx100-pinctrl" or 6*4882a593Smuzhiyun "lantiq,xrx200-pinctrl") 7*4882a593Smuzhiyun "lantiq,pinctrl-ase", (DEPRECATED: Use "lantiq,ase-pinctrl") 8*4882a593Smuzhiyun "lantiq,<chip>-pinctrl", where <chip> is: 9*4882a593Smuzhiyun "ase" (XWAY AMAZON Family) 10*4882a593Smuzhiyun "danube" (XWAY DANUBE Family) 11*4882a593Smuzhiyun "xrx100" (XWAY xRX100 Family) 12*4882a593Smuzhiyun "xrx200" (XWAY xRX200 Family) 13*4882a593Smuzhiyun "xrx300" (XWAY xRX300 Family) 14*4882a593Smuzhiyun- reg: Should contain the physical address and length of the gpio/pinmux 15*4882a593Smuzhiyun register range 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunPlease refer to pinctrl-bindings.txt in this directory for details of the 18*4882a593Smuzhiyuncommon pinctrl bindings used by client devices, including the meaning of the 19*4882a593Smuzhiyunphrase "pin configuration node". 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunLantiq's pin configuration nodes act as a container for an arbitrary number of 22*4882a593Smuzhiyunsubnodes. Each of these subnodes represents some desired configuration for a 23*4882a593Smuzhiyunpin, a group, or a list of pins or groups. This configuration can include the 24*4882a593Smuzhiyunmux function to select on those group(s), and two pin configuration parameters: 25*4882a593Smuzhiyunpull-up and open-drain 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunThe name of each subnode is not important as long as it is unique; all subnodes 28*4882a593Smuzhiyunshould be enumerated and processed purely based on their content. 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunEach subnode only affects those parameters that are explicitly listed. In 31*4882a593Smuzhiyunother words, a subnode that lists a mux function but no pin configuration 32*4882a593Smuzhiyunparameters implies no information about any pin configuration parameters. 33*4882a593SmuzhiyunSimilarly, a pin subnode that describes a pullup parameter implies no 34*4882a593Smuzhiyuninformation about e.g. the mux function. 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunWe support 2 types of nodes. 37*4882a593Smuzhiyun 38*4882a593SmuzhiyunDefinition of mux function groups: 39*4882a593Smuzhiyun 40*4882a593SmuzhiyunRequired subnode-properties: 41*4882a593Smuzhiyun- lantiq,groups : An array of strings. Each string contains the name of a group. 42*4882a593Smuzhiyun Valid values for these names are listed below. 43*4882a593Smuzhiyun- lantiq,function: A string containing the name of the function to mux to the 44*4882a593Smuzhiyun group. Valid values for function names are listed below. 45*4882a593Smuzhiyun 46*4882a593SmuzhiyunValid values for group and function names: 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunXWAY: (DEPRECATED: Use DANUBE) 49*4882a593Smuzhiyun mux groups: 50*4882a593Smuzhiyun exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1, 51*4882a593Smuzhiyun ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3, 52*4882a593Smuzhiyun spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, 53*4882a593Smuzhiyun gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, req1, req2, 54*4882a593Smuzhiyun req3 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun functions: 57*4882a593Smuzhiyun spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu 58*4882a593Smuzhiyun 59*4882a593SmuzhiyunXR9: ( DEPRECATED: Use xRX100/xRX200) 60*4882a593Smuzhiyun mux groups: 61*4882a593Smuzhiyun exin0, exin1, exin2, exin3, exin4, jtag, ebu a23, ebu a24, ebu a25, 62*4882a593Smuzhiyun ebu clk, ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, 63*4882a593Smuzhiyun nand rd, spi, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6, 64*4882a593Smuzhiyun asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1, 65*4882a593Smuzhiyun clkout2, clkout3, gnt1, gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio, 66*4882a593Smuzhiyun gphy0 led0, gphy0 led1, gphy0 led2, gphy1 led0, gphy1 led1, gphy1 led2 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun functions: 69*4882a593Smuzhiyun spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio, gphy 70*4882a593Smuzhiyun 71*4882a593SmuzhiyunAMAZON: 72*4882a593Smuzhiyun mux groups: 73*4882a593Smuzhiyun exin0, exin1, exin2, jtag, spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, 74*4882a593Smuzhiyun spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc, stp, gpt1, gpt2, gpt3, clkout0, 75*4882a593Smuzhiyun clkout1, clkout2, mdio, dfe led0, dfe led1, ephy led0, ephy led1, ephy led2 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun functions: 78*4882a593Smuzhiyun spi, asc, cgu, jtag, exin, stp, gpt, mdio, ephy, dfe 79*4882a593Smuzhiyun 80*4882a593SmuzhiyunDANUBE: 81*4882a593Smuzhiyun mux groups: 82*4882a593Smuzhiyun exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1, 83*4882a593Smuzhiyun ebu wait, nand ale, nand cs1, nand cle, spi_di, spi_do, spi_clk, spi_cs1, 84*4882a593Smuzhiyun spi_cs2, spi_cs3, spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi, 85*4882a593Smuzhiyun gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, 86*4882a593Smuzhiyun req1, req2, req3, dfe led0, dfe led1 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun functions: 89*4882a593Smuzhiyun spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, dfe 90*4882a593Smuzhiyun 91*4882a593SmuzhiyunxRX100: 92*4882a593Smuzhiyun mux groups: 93*4882a593Smuzhiyun exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk, 94*4882a593Smuzhiyun ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd, 95*4882a593Smuzhiyun spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5, 96*4882a593Smuzhiyun spi_cs6, asc0, asc0 cts rts, stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1, 97*4882a593Smuzhiyun clkout2, clkout3, gnt1, gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio, 98*4882a593Smuzhiyun dfe led0, dfe led1 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun functions: 101*4882a593Smuzhiyun spi, asc, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe 102*4882a593Smuzhiyun 103*4882a593SmuzhiyunxRX200: 104*4882a593Smuzhiyun mux groups: 105*4882a593Smuzhiyun exin0, exin1, exin2, exin3, exin4, ebu a23, ebu a24, ebu a25, ebu clk, 106*4882a593Smuzhiyun ebu cs1, ebu wait, nand ale, nand cs1, nand cle, nand rdy, nand rd, 107*4882a593Smuzhiyun spi_di, spi_do, spi_clk, spi_cs1, spi_cs2, spi_cs3, spi_cs4, spi_cs5, 108*4882a593Smuzhiyun spi_cs6, usif uart_rx, usif uart_tx, usif uart_rts, usif uart_cts, 109*4882a593Smuzhiyun usif uart_dtr, usif uart_dsr, usif uart_dcd, usif uart_ri, usif spi_di, 110*4882a593Smuzhiyun usif spi_do, usif spi_clk, usif spi_cs0, usif spi_cs1, usif spi_cs2, 111*4882a593Smuzhiyun stp, nmi, gpt1, gpt2, gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, 112*4882a593Smuzhiyun gnt2, gnt3, gnt4, req1, req2, req3, req4, mdio, dfe led0, dfe led1, 113*4882a593Smuzhiyun gphy0 led0, gphy0 led1, gphy0 led2, gphy1 led0, gphy1 led1, gphy1 led2 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun functions: 116*4882a593Smuzhiyun spi, usif, cgu, exin, stp, gpt, nmi, pci, ebu, mdio, dfe, gphy 117*4882a593Smuzhiyun 118*4882a593SmuzhiyunxRX300: 119*4882a593Smuzhiyun mux groups: 120*4882a593Smuzhiyun exin0, exin1, exin2, exin4, nand ale, nand cs0, nand cs1, nand cle, 121*4882a593Smuzhiyun nand rdy, nand rd, nand_d0, nand_d1, nand_d2, nand_d3, nand_d4, nand_d5, 122*4882a593Smuzhiyun nand_d6, nand_d7, nand_d1, nand wr, nand wp, nand se, spi_di, spi_do, 123*4882a593Smuzhiyun spi_clk, spi_cs1, spi_cs4, spi_cs6, usif uart_rx, usif uart_tx, 124*4882a593Smuzhiyun usif spi_di, usif spi_do, usif spi_clk, usif spi_cs0, stp, clkout2, 125*4882a593Smuzhiyun mdio, dfe led0, dfe led1, ephy0 led0, ephy0 led1, ephy1 led0, ephy1 led1 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun functions: 128*4882a593Smuzhiyun spi, usif, cgu, exin, stp, ebu, mdio, dfe, ephy 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun 131*4882a593SmuzhiyunDefinition of pin configurations: 132*4882a593Smuzhiyun 133*4882a593SmuzhiyunRequired subnode-properties: 134*4882a593Smuzhiyun- lantiq,pins : An array of strings. Each string contains the name of a pin. 135*4882a593Smuzhiyun Valid values for these names are listed below. 136*4882a593Smuzhiyun 137*4882a593SmuzhiyunOptional subnode-properties: 138*4882a593Smuzhiyun- lantiq,pull: Integer, representing the pull-down/up to apply to the pin. 139*4882a593Smuzhiyun 0: none, 1: down, 2: up. 140*4882a593Smuzhiyun- lantiq,open-drain: Boolean, enables open-drain on the defined pin. 141*4882a593Smuzhiyun 142*4882a593SmuzhiyunValid values for XWAY pin names: (DEPRECATED: Use DANUBE) 143*4882a593Smuzhiyun Pinconf pins can be referenced via the names io0-io31. 144*4882a593Smuzhiyun 145*4882a593SmuzhiyunValid values for XR9 pin names: (DEPRECATED: Use xrX100/xRX200) 146*4882a593Smuzhiyun Pinconf pins can be referenced via the names io0-io55. 147*4882a593Smuzhiyun 148*4882a593SmuzhiyunValid values for AMAZON pin names: 149*4882a593Smuzhiyun Pinconf pins can be referenced via the names io0-io31. 150*4882a593Smuzhiyun 151*4882a593SmuzhiyunValid values for DANUBE pin names: 152*4882a593Smuzhiyun Pinconf pins can be referenced via the names io0-io31. 153*4882a593Smuzhiyun 154*4882a593SmuzhiyunValid values for xRX100 pin names: 155*4882a593Smuzhiyun Pinconf pins can be referenced via the names io0-io55. 156*4882a593Smuzhiyun 157*4882a593SmuzhiyunValid values for xRX200 pin names: 158*4882a593Smuzhiyun Pinconf pins can be referenced via the names io0-io49. 159*4882a593Smuzhiyun 160*4882a593SmuzhiyunValid values for xRX300 pin names: 161*4882a593Smuzhiyun Pinconf pins can be referenced via the names io0-io1,io3-io6,io8-io11, 162*4882a593Smuzhiyun io13-io19,io23-io27,io34-io36, 163*4882a593Smuzhiyun io42-io43,io48-io61. 164*4882a593Smuzhiyun 165*4882a593SmuzhiyunExample: 166*4882a593Smuzhiyun gpio: pinmux@e100b10 { 167*4882a593Smuzhiyun compatible = "lantiq,danube-pinctrl"; 168*4882a593Smuzhiyun pinctrl-names = "default"; 169*4882a593Smuzhiyun pinctrl-0 = <&state_default>; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun #gpio-cells = <2>; 172*4882a593Smuzhiyun gpio-controller; 173*4882a593Smuzhiyun reg = <0xE100B10 0xA0>; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun state_default: pinmux { 176*4882a593Smuzhiyun stp { 177*4882a593Smuzhiyun lantiq,groups = "stp"; 178*4882a593Smuzhiyun lantiq,function = "stp"; 179*4882a593Smuzhiyun }; 180*4882a593Smuzhiyun pci { 181*4882a593Smuzhiyun lantiq,groups = "gnt1"; 182*4882a593Smuzhiyun lantiq,function = "pci"; 183*4882a593Smuzhiyun }; 184*4882a593Smuzhiyun conf_out { 185*4882a593Smuzhiyun lantiq,pins = "io4", "io5", "io6"; /* stp */ 186*4882a593Smuzhiyun lantiq,open-drain; 187*4882a593Smuzhiyun lantiq,pull = <0>; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun }; 190*4882a593Smuzhiyun }; 191*4882a593Smuzhiyun 192