1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/pinctrl/intel,lgm-io.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Intel Lightning Mountain SoC pinmux & GPIO controller binding 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Rahul Tanwar <rahul.tanwar@linux.intel.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun Pinmux & GPIO controller controls pin multiplexing & configuration including 14*4882a593Smuzhiyun GPIO function selection & GPIO attributes configuration. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunproperties: 17*4882a593Smuzhiyun compatible: 18*4882a593Smuzhiyun const: intel,lgm-io 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun reg: 21*4882a593Smuzhiyun maxItems: 1 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun# Client device subnode's properties 24*4882a593SmuzhiyunpatternProperties: 25*4882a593Smuzhiyun '-pins$': 26*4882a593Smuzhiyun type: object 27*4882a593Smuzhiyun description: 28*4882a593Smuzhiyun Pinctrl node's client devices use subnodes for desired pin configuration. 29*4882a593Smuzhiyun Client device subnodes use below standard properties. 30*4882a593Smuzhiyun $ref: pinmux-node.yaml# 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun properties: 33*4882a593Smuzhiyun function: true 34*4882a593Smuzhiyun groups: true 35*4882a593Smuzhiyun pins: true 36*4882a593Smuzhiyun pinmux: true 37*4882a593Smuzhiyun bias-pull-up: true 38*4882a593Smuzhiyun bias-pull-down: true 39*4882a593Smuzhiyun drive-strength: true 40*4882a593Smuzhiyun slew-rate: true 41*4882a593Smuzhiyun drive-open-drain: true 42*4882a593Smuzhiyun output-enable: true 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun required: 45*4882a593Smuzhiyun - function 46*4882a593Smuzhiyun - groups 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun additionalProperties: false 49*4882a593Smuzhiyun 50*4882a593Smuzhiyunrequired: 51*4882a593Smuzhiyun - compatible 52*4882a593Smuzhiyun - reg 53*4882a593Smuzhiyun 54*4882a593SmuzhiyunadditionalProperties: false 55*4882a593Smuzhiyun 56*4882a593Smuzhiyunexamples: 57*4882a593Smuzhiyun # Pinmux controller node 58*4882a593Smuzhiyun - | 59*4882a593Smuzhiyun pinctrl: pinctrl@e2880000 { 60*4882a593Smuzhiyun compatible = "intel,lgm-io"; 61*4882a593Smuzhiyun reg = <0xe2880000 0x100000>; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun uart0-pins { 64*4882a593Smuzhiyun pins = <64>, /* UART_RX0 */ 65*4882a593Smuzhiyun <65>; /* UART_TX0 */ 66*4882a593Smuzhiyun function = "CONSOLE_UART0"; 67*4882a593Smuzhiyun pinmux = <1>, 68*4882a593Smuzhiyun <1>; 69*4882a593Smuzhiyun groups = "CONSOLE_UART0"; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun... 74