xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/img,pistachio-pinctrl.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunImagination Technologies Pistachio SoC pin controllers
2*4882a593Smuzhiyun======================================================
3*4882a593Smuzhiyun
4*4882a593SmuzhiyunThe pin controllers on Pistachio are a combined GPIO controller, (GPIO)
5*4882a593Smuzhiyuninterrupt controller, and pinmux + pinconf device. The system ("east") pin
6*4882a593Smuzhiyuncontroller on Pistachio has 99 pins, 90 of which are MFIOs which can be
7*4882a593Smuzhiyunconfigured as GPIOs. The 90 GPIOs are divided into 6 banks of up to 16 GPIOs
8*4882a593Smuzhiyuneach. The GPIO banks are represented as sub-nodes of the pad controller node.
9*4882a593Smuzhiyun
10*4882a593SmuzhiyunPlease refer to pinctrl-bindings.txt, ../gpio/gpio.txt, and
11*4882a593Smuzhiyun../interrupt-controller/interrupts.txt for generic information regarding
12*4882a593Smuzhiyunpin controller, GPIO, and interrupt bindings.
13*4882a593Smuzhiyun
14*4882a593SmuzhiyunRequired properties for pin controller node:
15*4882a593Smuzhiyun--------------------------------------------
16*4882a593Smuzhiyun - compatible: "img,pistachio-system-pinctrl".
17*4882a593Smuzhiyun - reg: Address range of the pinctrl registers.
18*4882a593Smuzhiyun
19*4882a593SmuzhiyunRequired properties for GPIO bank sub-nodes:
20*4882a593Smuzhiyun--------------------------------------------
21*4882a593Smuzhiyun - interrupts: Interrupt line for the GPIO bank.
22*4882a593Smuzhiyun - gpio-controller: Indicates the device is a GPIO controller.
23*4882a593Smuzhiyun - #gpio-cells: Must be two. The first cell is the GPIO pin number and the
24*4882a593Smuzhiyun   second cell indicates the polarity. See <dt-bindings/gpio/gpio.h> for
25*4882a593Smuzhiyun   a list of possible values.
26*4882a593Smuzhiyun - interrupt-controller: Indicates the device is an interrupt controller.
27*4882a593Smuzhiyun - #interrupt-cells: Must be two. The first cell is the GPIO pin number and
28*4882a593Smuzhiyun   the second cell encodes the interrupt flags. See
29*4882a593Smuzhiyun   <dt-bindings/interrupt-controller/irq.h> for a list of valid flags.
30*4882a593Smuzhiyun
31*4882a593SmuzhiyunNote that the N GPIO bank sub-nodes *must* be named gpio0, gpio1, ... gpioN-1.
32*4882a593Smuzhiyun
33*4882a593SmuzhiyunRequired properties for pin configuration sub-nodes:
34*4882a593Smuzhiyun----------------------------------------------------
35*4882a593Smuzhiyun - pins: List of pins to which the configuration applies. See below for a
36*4882a593Smuzhiyun   list of possible pins.
37*4882a593Smuzhiyun
38*4882a593SmuzhiyunOptional properties for pin configuration sub-nodes:
39*4882a593Smuzhiyun----------------------------------------------------
40*4882a593Smuzhiyun - function: Mux function for the specified pins. This is not applicable for
41*4882a593Smuzhiyun   non-MFIO pins. See below for a list of valid functions for each pin.
42*4882a593Smuzhiyun - bias-high-impedance: Enable high-impedance mode.
43*4882a593Smuzhiyun - bias-pull-up: Enable weak pull-up.
44*4882a593Smuzhiyun - bias-pull-down: Enable weak pull-down.
45*4882a593Smuzhiyun - bias-bus-hold: Enable bus-keeper mode.
46*4882a593Smuzhiyun - drive-strength: Drive strength in mA. Supported values: 2, 4, 8, 12.
47*4882a593Smuzhiyun - input-schmitt-enable: Enable Schmitt trigger.
48*4882a593Smuzhiyun - input-schmitt-disable: Disable Schmitt trigger.
49*4882a593Smuzhiyun - slew-rate: Slew rate control. 0 for slow, 1 for fast.
50*4882a593Smuzhiyun
51*4882a593SmuzhiyunPin		Functions
52*4882a593Smuzhiyun---		---------
53*4882a593Smuzhiyunmfio0		spim1
54*4882a593Smuzhiyunmfio1		spim1, spim0, uart1
55*4882a593Smuzhiyunmfio2		spim1, spim0, uart1
56*4882a593Smuzhiyunmfio3		spim1
57*4882a593Smuzhiyunmfio4		spim1
58*4882a593Smuzhiyunmfio5		spim1
59*4882a593Smuzhiyunmfio6		spim1
60*4882a593Smuzhiyunmfio7		spim1
61*4882a593Smuzhiyunmfio8		spim0
62*4882a593Smuzhiyunmfio9		spim0
63*4882a593Smuzhiyunmfio10		spim0
64*4882a593Smuzhiyunmfio11		spis
65*4882a593Smuzhiyunmfio12		spis
66*4882a593Smuzhiyunmfio13		spis
67*4882a593Smuzhiyunmfio14		spis
68*4882a593Smuzhiyunmfio15		sdhost, mips_trace_clk, mips_trace_data
69*4882a593Smuzhiyunmfio16		sdhost, mips_trace_dint, mips_trace_data
70*4882a593Smuzhiyunmfio17		sdhost, mips_trace_trigout, mips_trace_data
71*4882a593Smuzhiyunmfio18		sdhost, mips_trace_trigin, mips_trace_data
72*4882a593Smuzhiyunmfio19		sdhost, mips_trace_dm, mips_trace_data
73*4882a593Smuzhiyunmfio20		sdhost, mips_trace_probe_n, mips_trace_data
74*4882a593Smuzhiyunmfio21		sdhost, mips_trace_data
75*4882a593Smuzhiyunmfio22		sdhost, mips_trace_data
76*4882a593Smuzhiyunmfio23		sdhost
77*4882a593Smuzhiyunmfio24		sdhost
78*4882a593Smuzhiyunmfio25		sdhost
79*4882a593Smuzhiyunmfio26		sdhost
80*4882a593Smuzhiyunmfio27		sdhost
81*4882a593Smuzhiyunmfio28		i2c0, spim0
82*4882a593Smuzhiyunmfio29		i2c0, spim0
83*4882a593Smuzhiyunmfio30		i2c1, spim0
84*4882a593Smuzhiyunmfio31		i2c1, spim1
85*4882a593Smuzhiyunmfio32		i2c2
86*4882a593Smuzhiyunmfio33		i2c2
87*4882a593Smuzhiyunmfio34		i2c3
88*4882a593Smuzhiyunmfio35		i2c3
89*4882a593Smuzhiyunmfio36		i2s_out, audio_clk_in
90*4882a593Smuzhiyunmfio37		i2s_out, debug_raw_cca_ind
91*4882a593Smuzhiyunmfio38		i2s_out, debug_ed_sec20_cca_ind
92*4882a593Smuzhiyunmfio39		i2s_out, debug_ed_sec40_cca_ind
93*4882a593Smuzhiyunmfio40		i2s_out, debug_agc_done_0
94*4882a593Smuzhiyunmfio41		i2s_out, debug_agc_done_1
95*4882a593Smuzhiyunmfio42		i2s_out, debug_ed_cca_ind
96*4882a593Smuzhiyunmfio43		i2s_out, debug_s2l_done
97*4882a593Smuzhiyunmfio44		i2s_out
98*4882a593Smuzhiyunmfio45		i2s_dac_clk, audio_sync
99*4882a593Smuzhiyunmfio46		audio_trigger
100*4882a593Smuzhiyunmfio47		i2s_in
101*4882a593Smuzhiyunmfio48		i2s_in
102*4882a593Smuzhiyunmfio49		i2s_in
103*4882a593Smuzhiyunmfio50		i2s_in
104*4882a593Smuzhiyunmfio51		i2s_in
105*4882a593Smuzhiyunmfio52		i2s_in
106*4882a593Smuzhiyunmfio53		i2s_in
107*4882a593Smuzhiyunmfio54		i2s_in, spdif_in
108*4882a593Smuzhiyunmfio55		uart0, spim0, spim1
109*4882a593Smuzhiyunmfio56		uart0, spim0, spim1
110*4882a593Smuzhiyunmfio57		uart0, spim0, spim1
111*4882a593Smuzhiyunmfio58		uart0, spim1
112*4882a593Smuzhiyunmfio59		uart1
113*4882a593Smuzhiyunmfio60		uart1
114*4882a593Smuzhiyunmfio61		spdif_out
115*4882a593Smuzhiyunmfio62		spdif_in
116*4882a593Smuzhiyunmfio63		eth, mips_trace_clk, mips_trace_data
117*4882a593Smuzhiyunmfio64		eth, mips_trace_dint, mips_trace_data
118*4882a593Smuzhiyunmfio65		eth, mips_trace_trigout, mips_trace_data
119*4882a593Smuzhiyunmfio66		eth, mips_trace_trigin, mips_trace_data
120*4882a593Smuzhiyunmfio67		eth, mips_trace_dm, mips_trace_data
121*4882a593Smuzhiyunmfio68		eth, mips_trace_probe_n, mips_trace_data
122*4882a593Smuzhiyunmfio69		eth, mips_trace_data
123*4882a593Smuzhiyunmfio70		eth, mips_trace_data
124*4882a593Smuzhiyunmfio71		eth
125*4882a593Smuzhiyunmfio72		ir
126*4882a593Smuzhiyunmfio73		pwmpdm, mips_trace_clk, sram_debug
127*4882a593Smuzhiyunmfio74		pwmpdm, mips_trace_dint, sram_debug
128*4882a593Smuzhiyunmfio75		pwmpdm, mips_trace_trigout, rom_debug
129*4882a593Smuzhiyunmfio76		pwmpdm, mips_trace_trigin, rom_debug
130*4882a593Smuzhiyunmfio77		mdc_debug, mips_trace_dm, rpu_debug
131*4882a593Smuzhiyunmfio78		mdc_debug, mips_trace_probe_n, rpu_debug
132*4882a593Smuzhiyunmfio79		ddr_debug, mips_trace_data, mips_debug
133*4882a593Smuzhiyunmfio80		ddr_debug, mips_trace_data, mips_debug
134*4882a593Smuzhiyunmfio81		dreq0, mips_trace_data, eth_debug
135*4882a593Smuzhiyunmfio82		dreq1, mips_trace_data, eth_debug
136*4882a593Smuzhiyunmfio83		mips_pll_lock, mips_trace_data, usb_debug
137*4882a593Smuzhiyunmfio84		audio_pll_lock, mips_trace_data, usb_debug
138*4882a593Smuzhiyunmfio85		rpu_v_pll_lock, mips_trace_data, sdhost_debug
139*4882a593Smuzhiyunmfio86		rpu_l_pll_lock, mips_trace_data, sdhost_debug
140*4882a593Smuzhiyunmfio87		sys_pll_lock, dreq2, socif_debug
141*4882a593Smuzhiyunmfio88		wifi_pll_lock, dreq3, socif_debug
142*4882a593Smuzhiyunmfio89		bt_pll_lock, dreq4, dreq5
143*4882a593Smuzhiyuntck
144*4882a593Smuzhiyuntrstn
145*4882a593Smuzhiyuntdi
146*4882a593Smuzhiyuntms
147*4882a593Smuzhiyuntdo
148*4882a593Smuzhiyunjtag_comply
149*4882a593Smuzhiyunsafe_mode
150*4882a593Smuzhiyunpor_disable
151*4882a593Smuzhiyunresetn
152*4882a593Smuzhiyun
153*4882a593SmuzhiyunExample:
154*4882a593Smuzhiyun--------
155*4882a593Smuzhiyunpinctrl@18101c00 {
156*4882a593Smuzhiyun	compatible = "img,pistachio-system-pinctrl";
157*4882a593Smuzhiyun	reg = <0x18101C00 0x400>;
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun	gpio0: gpio0 {
160*4882a593Smuzhiyun		interrupts = <GIC_SHARED 71 IRQ_TYPE_LEVEL_HIGH>;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun		gpio-controller;
163*4882a593Smuzhiyun		#gpio-cells = <2>;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun		interrupt-controller;
166*4882a593Smuzhiyun		#interrupt-cells = <2>;
167*4882a593Smuzhiyun	};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun	...
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun	gpio5: gpio5 {
172*4882a593Smuzhiyun		interrupts = <GIC_SHARED 76 IRQ_TYPE_LEVEL_HIGH>;
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun		gpio-controller;
175*4882a593Smuzhiyun		#gpio-cells = <2>;
176*4882a593Smuzhiyun
177*4882a593Smuzhiyun		interrupt-controller;
178*4882a593Smuzhiyun		#interrupt-cells = <2>;
179*4882a593Smuzhiyun	};
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun	...
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun	uart0_xfer: uart0-xfer {
184*4882a593Smuzhiyun		uart0-rxd {
185*4882a593Smuzhiyun			pins = "mfio55";
186*4882a593Smuzhiyun			function = "uart0";
187*4882a593Smuzhiyun		};
188*4882a593Smuzhiyun		uart0-txd {
189*4882a593Smuzhiyun			pins = "mfio56";
190*4882a593Smuzhiyun			function = "uart0";
191*4882a593Smuzhiyun		};
192*4882a593Smuzhiyun	};
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun	uart0_rts_cts: uart0-rts-cts {
195*4882a593Smuzhiyun		uart0-rts {
196*4882a593Smuzhiyun			  pins = "mfio57";
197*4882a593Smuzhiyun			  function = "uart0";
198*4882a593Smuzhiyun		};
199*4882a593Smuzhiyun		uart0-cts {
200*4882a593Smuzhiyun			  pins = "mfio58";
201*4882a593Smuzhiyun			  function = "uart0";
202*4882a593Smuzhiyun		};
203*4882a593Smuzhiyun	};
204*4882a593Smuzhiyun};
205*4882a593Smuzhiyun
206*4882a593Smuzhiyunuart@... {
207*4882a593Smuzhiyun	...
208*4882a593Smuzhiyun	pinctrl-names = "default";
209*4882a593Smuzhiyun	pinctrl-0 = <&uart0_xfer>, <&uart0_rts_cts>;
210*4882a593Smuzhiyun	...
211*4882a593Smuzhiyun};
212*4882a593Smuzhiyun
213*4882a593Smuzhiyunusb_vbus: fixed-regulator {
214*4882a593Smuzhiyun	...
215*4882a593Smuzhiyun	gpio = <&gpio5 6 GPIO_ACTIVE_HIGH>;
216*4882a593Smuzhiyun	...
217*4882a593Smuzhiyun};
218