1*4882a593Smuzhiyun* Freescale MXS Pin Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe pins controlled by mxs pin controller are organized in banks, each bank 4*4882a593Smuzhiyunhas 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th 5*4882a593Smuzhiyunfunction is GPIO. The configuration on the pins includes drive strength, 6*4882a593Smuzhiyunvoltage and pull-up. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties: 9*4882a593Smuzhiyun- compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl" 10*4882a593Smuzhiyun- reg: Should contain the register physical address and length for the 11*4882a593Smuzhiyun pin controller. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunPlease refer to pinctrl-bindings.txt in this directory for details of the 14*4882a593Smuzhiyuncommon pinctrl bindings used by client devices. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunThe node of mxs pin controller acts as a container for an arbitrary number of 17*4882a593Smuzhiyunsubnodes. Each of these subnodes represents some desired configuration for 18*4882a593Smuzhiyuna group of pins, and only affects those parameters that are explicitly listed. 19*4882a593SmuzhiyunIn other words, a subnode that describes a drive strength parameter implies no 20*4882a593Smuzhiyuninformation about pull-up. For this reason, even seemingly boolean values are 21*4882a593Smuzhiyunactually tristates in this binding: unspecified, off, or on. Unspecified is 22*4882a593Smuzhiyunrepresented as an absent property, and off/on are represented as integer 23*4882a593Smuzhiyunvalues 0 and 1. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunThose subnodes under mxs pin controller node will fall into two categories. 26*4882a593SmuzhiyunOne is to set up a group of pins for a function, both mux selection and pin 27*4882a593Smuzhiyunconfigurations, and it's called group node in the binding document. The other 28*4882a593Smuzhiyunone is to adjust the pin configuration for some particular pins that need a 29*4882a593Smuzhiyundifferent configuration than what is defined in group node. The binding 30*4882a593Smuzhiyundocument calls this type of node config node. 31*4882a593Smuzhiyun 32*4882a593SmuzhiyunOn mxs, there is no hardware pin group. The pin group in this binding only 33*4882a593Smuzhiyunmeans a group of pins put together for particular peripheral to work in 34*4882a593Smuzhiyunparticular function, like SSP0 functioning as mmc0-8bit. That said, the 35*4882a593Smuzhiyungroup node should include all the pins needed for one function rather than 36*4882a593Smuzhiyunhaving these pins defined in several group nodes. It also means each of 37*4882a593Smuzhiyun"pinctrl-*" phandle in client device node should only have one group node 38*4882a593Smuzhiyunpointed in there, while the phandle can have multiple config node referenced 39*4882a593Smuzhiyunthere to adjust configurations for some pins in the group. 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunRequired subnode-properties: 42*4882a593Smuzhiyun- fsl,pinmux-ids: An integer array. Each integer in the array specify a pin 43*4882a593Smuzhiyun with given mux function, with bank, pin and mux packed as below. 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun [15..12] : bank number 46*4882a593Smuzhiyun [11..4] : pin number 47*4882a593Smuzhiyun [3..0] : mux selection 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun This integer with mux selection packed is used as an entity by both group 50*4882a593Smuzhiyun and config nodes to identify a pin. The mux selection in the integer takes 51*4882a593Smuzhiyun effects only on group node, and will get ignored by driver with config node, 52*4882a593Smuzhiyun since config node is only meant to set up pin configurations. 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun Valid values for these integers are listed below. 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun- reg: Should be the index of the group nodes for same function. This property 57*4882a593Smuzhiyun is required only for group nodes, and should not be present in any config 58*4882a593Smuzhiyun nodes. 59*4882a593Smuzhiyun 60*4882a593SmuzhiyunOptional subnode-properties: 61*4882a593Smuzhiyun- fsl,drive-strength: Integer. 62*4882a593Smuzhiyun 0: MXS_DRIVE_4mA 63*4882a593Smuzhiyun 1: MXS_DRIVE_8mA 64*4882a593Smuzhiyun 2: MXS_DRIVE_12mA 65*4882a593Smuzhiyun 3: MXS_DRIVE_16mA 66*4882a593Smuzhiyun- fsl,voltage: Integer. 67*4882a593Smuzhiyun 0: MXS_VOLTAGE_LOW - 1.8 V 68*4882a593Smuzhiyun 1: MXS_VOLTAGE_HIGH - 3.3 V 69*4882a593Smuzhiyun- fsl,pull-up: Integer. 70*4882a593Smuzhiyun 0: MXS_PULL_DISABLE - Disable the internal pull-up 71*4882a593Smuzhiyun 1: MXS_PULL_ENABLE - Enable the internal pull-up 72*4882a593Smuzhiyun 73*4882a593SmuzhiyunNote that when enabling the pull-up, the internal pad keeper gets disabled. 74*4882a593SmuzhiyunAlso, some pins doesn't have a pull up, in that case, setting the fsl,pull-up 75*4882a593Smuzhiyunwill only disable the internal pad keeper. 76*4882a593Smuzhiyun 77*4882a593SmuzhiyunExamples: 78*4882a593Smuzhiyun 79*4882a593Smuzhiyunpinctrl@80018000 { 80*4882a593Smuzhiyun #address-cells = <1>; 81*4882a593Smuzhiyun #size-cells = <0>; 82*4882a593Smuzhiyun compatible = "fsl,imx28-pinctrl"; 83*4882a593Smuzhiyun reg = <0x80018000 2000>; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun mmc0_8bit_pins_a: mmc0-8bit@0 { 86*4882a593Smuzhiyun reg = <0>; 87*4882a593Smuzhiyun fsl,pinmux-ids = < 88*4882a593Smuzhiyun MX28_PAD_SSP0_DATA0__SSP0_D0 89*4882a593Smuzhiyun MX28_PAD_SSP0_DATA1__SSP0_D1 90*4882a593Smuzhiyun MX28_PAD_SSP0_DATA2__SSP0_D2 91*4882a593Smuzhiyun MX28_PAD_SSP0_DATA3__SSP0_D3 92*4882a593Smuzhiyun MX28_PAD_SSP0_DATA4__SSP0_D4 93*4882a593Smuzhiyun MX28_PAD_SSP0_DATA5__SSP0_D5 94*4882a593Smuzhiyun MX28_PAD_SSP0_DATA6__SSP0_D6 95*4882a593Smuzhiyun MX28_PAD_SSP0_DATA7__SSP0_D7 96*4882a593Smuzhiyun MX28_PAD_SSP0_CMD__SSP0_CMD 97*4882a593Smuzhiyun MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT 98*4882a593Smuzhiyun MX28_PAD_SSP0_SCK__SSP0_SCK 99*4882a593Smuzhiyun >; 100*4882a593Smuzhiyun fsl,drive-strength = <MXS_DRIVE_4mA>; 101*4882a593Smuzhiyun fsl,voltage = <MXS_VOLTAGE_HIGH>; 102*4882a593Smuzhiyun fsl,pull-up = <MXS_PULL_ENABLE>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun mmc_cd_cfg: mmc-cd-cfg { 106*4882a593Smuzhiyun fsl,pinmux-ids = <MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT>; 107*4882a593Smuzhiyun fsl,pull-up = <MXS_PULL_DISABLE>; 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun mmc_sck_cfg: mmc-sck-cfg { 111*4882a593Smuzhiyun fsl,pinmux-ids = <MX28_PAD_SSP0_SCK__SSP0_SCK>; 112*4882a593Smuzhiyun fsl,drive-strength = <MXS_DRIVE_12mA>; 113*4882a593Smuzhiyun fsl,pull-up = <MXS_PULL_DISABLE>; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun}; 116*4882a593Smuzhiyun 117*4882a593SmuzhiyunIn this example, group node mmc0-8bit defines a group of pins for mxs SSP0 118*4882a593Smuzhiyunto function as a 8-bit mmc device, with 8mA, 3.3V and pull-up configurations 119*4882a593Smuzhiyunapplied on all these pins. And config nodes mmc-cd-cfg and mmc-sck-cfg are 120*4882a593Smuzhiyunadjusting the configuration for pins card-detection and clock from what group 121*4882a593Smuzhiyunnode mmc0-8bit defines. Only the configuration properties to be adjusted need 122*4882a593Smuzhiyunto be listed in the config nodes. 123*4882a593Smuzhiyun 124*4882a593SmuzhiyunValid values for i.MX28/i.MX23 pinmux-id are defined in 125*4882a593Smuzhiyunarch/arm/boot/dts/imx28-pinfunc.h and arch/arm/boot/dts/imx23-pinfunc.h. 126*4882a593SmuzhiyunThe definitions for the padconfig properties can be found in 127*4882a593Smuzhiyunarch/arm/boot/dts/mxs-pinfunc.h. 128