1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mn-pinctrl.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Freescale IMX8MN IOMUX Controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Anson Huang <Anson.Huang@nxp.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: 13*4882a593Smuzhiyun Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory 14*4882a593Smuzhiyun for common binding part and usage. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunproperties: 17*4882a593Smuzhiyun compatible: 18*4882a593Smuzhiyun const: fsl,imx8mn-iomuxc 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun reg: 21*4882a593Smuzhiyun maxItems: 1 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun# Client device subnode's properties 24*4882a593SmuzhiyunpatternProperties: 25*4882a593Smuzhiyun 'grp$': 26*4882a593Smuzhiyun type: object 27*4882a593Smuzhiyun description: 28*4882a593Smuzhiyun Pinctrl node's client devices use subnodes for desired pin configuration. 29*4882a593Smuzhiyun Client device subnodes use below standard properties. 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun properties: 32*4882a593Smuzhiyun fsl,pins: 33*4882a593Smuzhiyun description: 34*4882a593Smuzhiyun each entry consists of 6 integers and represents the mux and config 35*4882a593Smuzhiyun setting for one pin. The first 5 integers <mux_reg conf_reg input_reg 36*4882a593Smuzhiyun mux_val input_val> are specified using a PIN_FUNC_ID macro, which can 37*4882a593Smuzhiyun be found in <arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h>. The last 38*4882a593Smuzhiyun integer CONFIG is the pad setting value like pull-up on this pin. Please 39*4882a593Smuzhiyun refer to i.MX8M Nano Reference Manual for detailed CONFIG settings. 40*4882a593Smuzhiyun $ref: /schemas/types.yaml#/definitions/uint32-matrix 41*4882a593Smuzhiyun items: 42*4882a593Smuzhiyun items: 43*4882a593Smuzhiyun - description: | 44*4882a593Smuzhiyun "mux_reg" indicates the offset of mux register. 45*4882a593Smuzhiyun - description: | 46*4882a593Smuzhiyun "conf_reg" indicates the offset of pad configuration register. 47*4882a593Smuzhiyun - description: | 48*4882a593Smuzhiyun "input_reg" indicates the offset of select input register. 49*4882a593Smuzhiyun - description: | 50*4882a593Smuzhiyun "mux_val" indicates the mux value to be applied. 51*4882a593Smuzhiyun - description: | 52*4882a593Smuzhiyun "input_val" indicates the select input value to be applied. 53*4882a593Smuzhiyun - description: | 54*4882a593Smuzhiyun "pad_setting" indicates the pad configuration value to be applied. 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun required: 57*4882a593Smuzhiyun - fsl,pins 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun additionalProperties: false 60*4882a593Smuzhiyun 61*4882a593Smuzhiyunrequired: 62*4882a593Smuzhiyun - compatible 63*4882a593Smuzhiyun - reg 64*4882a593Smuzhiyun 65*4882a593SmuzhiyunadditionalProperties: false 66*4882a593Smuzhiyun 67*4882a593Smuzhiyunexamples: 68*4882a593Smuzhiyun # Pinmux controller node 69*4882a593Smuzhiyun - | 70*4882a593Smuzhiyun iomuxc: pinctrl@30330000 { 71*4882a593Smuzhiyun compatible = "fsl,imx8mn-iomuxc"; 72*4882a593Smuzhiyun reg = <0x30330000 0x10000>; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun pinctrl_uart2: uart2grp { 75*4882a593Smuzhiyun fsl,pins = 76*4882a593Smuzhiyun <0x23C 0x4A4 0x4FC 0x0 0x0 0x140>, 77*4882a593Smuzhiyun <0x240 0x4A8 0x000 0x0 0x0 0x140>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun... 82