1*4882a593Smuzhiyun* Freescale i.MX7ULP IOMUX Controller 2*4882a593Smuzhiyun 3*4882a593Smuzhiyuni.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7 4*4882a593Smuzhiyunports and IOMUXC DDR for DDR interface. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunNote: 7*4882a593SmuzhiyunThis binding doc is only for the IOMUXC1 support in A7 Domain and it only 8*4882a593Smuzhiyunsupports generic pin config. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunPlease refer to fsl,imx-pinctrl.txt in this directory for common binding 11*4882a593Smuzhiyunpart and usage. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunRequired properties: 14*4882a593Smuzhiyun- compatible: "fsl,imx7ulp-iomuxc1". 15*4882a593Smuzhiyun- fsl,pins: Each entry consists of 5 integers which represents the mux 16*4882a593Smuzhiyun and config setting for one pin. The first 4 integers 17*4882a593Smuzhiyun <mux_conf_reg input_reg mux_mode input_val> are specified 18*4882a593Smuzhiyun using a PIN_FUNC_ID macro, which can be found in 19*4882a593Smuzhiyun imx7ulp-pinfunc.h in the device tree source folder. 20*4882a593Smuzhiyun The last integer CONFIG is the pad setting value like 21*4882a593Smuzhiyun pull-up on this pin. 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun Please refer to i.MX7ULP Reference Manual for detailed 24*4882a593Smuzhiyun CONFIG settings. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunCONFIG bits definition: 27*4882a593SmuzhiyunPAD_CTL_OBE (1 << 17) 28*4882a593SmuzhiyunPAD_CTL_IBE (1 << 16) 29*4882a593SmuzhiyunPAD_CTL_LK (1 << 16) 30*4882a593SmuzhiyunPAD_CTL_DSE_HI (1 << 6) 31*4882a593SmuzhiyunPAD_CTL_DSE_STD (0 << 6) 32*4882a593SmuzhiyunPAD_CTL_ODE (1 << 5) 33*4882a593SmuzhiyunPAD_CTL_PUSH_PULL (0 << 5) 34*4882a593SmuzhiyunPAD_CTL_SRE_SLOW (1 << 2) 35*4882a593SmuzhiyunPAD_CTL_SRE_STD (0 << 2) 36*4882a593SmuzhiyunPAD_CTL_PE (1 << 0) 37*4882a593Smuzhiyun 38*4882a593SmuzhiyunExamples: 39*4882a593Smuzhiyun#include "imx7ulp-pinfunc.h" 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun/* Pin Controller Node */ 42*4882a593Smuzhiyuniomuxc1: pinctrl@40ac0000 { 43*4882a593Smuzhiyun compatible = "fsl,imx7ulp-iomuxc1"; 44*4882a593Smuzhiyun reg = <0x40ac0000 0x1000>; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* Pin Configuration Node */ 47*4882a593Smuzhiyun pinctrl_lpuart4: lpuart4grp { 48*4882a593Smuzhiyun fsl,pins = < 49*4882a593Smuzhiyun IMX7ULP_PAD_PTC3__LPUART4_RX 0x1 50*4882a593Smuzhiyun IMX7ULP_PAD_PTC2__LPUART4_TX 0x1 51*4882a593Smuzhiyun >; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun}; 54