1*4882a593Smuzhiyun* Freescale i.MX7 Dual IOMUX Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyuniMX7D supports two iomuxc controllers, fsl,imx7d-iomuxc controller is similar 4*4882a593Smuzhiyunas previous iMX SoC generation and fsl,imx7d-iomuxc-lpsr which provides low 5*4882a593Smuzhiyunpower state retention capabilities on gpios that are part of iomuxc-lpsr 6*4882a593Smuzhiyun(GPIO1_IO7..GPIO1_IO0). While iomuxc-lpsr provides its own set of registers for 7*4882a593Smuzhiyunmux and pad control settings, it shares the input select register from main 8*4882a593Smuzhiyuniomuxc controller for daisy chain settings, the fsl,input-sel property extends 9*4882a593Smuzhiyunfsl,imx-pinctrl driver to support iomuxc-lpsr controller. 10*4882a593Smuzhiyun 11*4882a593Smuzhiyuniomuxc_lpsr: iomuxc-lpsr@302c0000 { 12*4882a593Smuzhiyun compatible = "fsl,imx7d-iomuxc-lpsr"; 13*4882a593Smuzhiyun reg = <0x302c0000 0x10000>; 14*4882a593Smuzhiyun fsl,input-sel = <&iomuxc>; 15*4882a593Smuzhiyun}; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyuniomuxc: iomuxc@30330000 { 18*4882a593Smuzhiyun compatible = "fsl,imx7d-iomuxc"; 19*4882a593Smuzhiyun reg = <0x30330000 0x10000>; 20*4882a593Smuzhiyun}; 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunPeripherals using pads from iomuxc-lpsr support low state retention power 23*4882a593Smuzhiyunstate, under LPSR mode GPIO's state of pads are retain. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunPlease refer to fsl,imx-pinctrl.txt in this directory for common binding part 26*4882a593Smuzhiyunand usage. 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunRequired properties: 29*4882a593Smuzhiyun- compatible: "fsl,imx7d-iomuxc" for main IOMUXC controller, or 30*4882a593Smuzhiyun "fsl,imx7d-iomuxc-lpsr" for Low Power State Retention IOMUXC controller. 31*4882a593Smuzhiyun- fsl,pins: each entry consists of 6 integers and represents the mux and config 32*4882a593Smuzhiyun setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val 33*4882a593Smuzhiyun input_val> are specified using a PIN_FUNC_ID macro, which can be found in 34*4882a593Smuzhiyun imx7d-pinfunc.h under device tree source folder. The last integer CONFIG is 35*4882a593Smuzhiyun the pad setting value like pull-up on this pin. Please refer to i.MX7 Dual 36*4882a593Smuzhiyun Reference Manual for detailed CONFIG settings. 37*4882a593Smuzhiyun- fsl,input-sel: required property for iomuxc-lpsr controller, this property is 38*4882a593Smuzhiyun a phandle for main iomuxc controller which shares the input select register for 39*4882a593Smuzhiyun daisy chain settings. 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunCONFIG bits definition: 42*4882a593SmuzhiyunPAD_CTL_PUS_100K_DOWN (0 << 5) 43*4882a593SmuzhiyunPAD_CTL_PUS_5K_UP (1 << 5) 44*4882a593SmuzhiyunPAD_CTL_PUS_47K_UP (2 << 5) 45*4882a593SmuzhiyunPAD_CTL_PUS_100K_UP (3 << 5) 46*4882a593SmuzhiyunPAD_CTL_PUE (1 << 4) 47*4882a593SmuzhiyunPAD_CTL_HYS (1 << 3) 48*4882a593SmuzhiyunPAD_CTL_SRE_SLOW (1 << 2) 49*4882a593SmuzhiyunPAD_CTL_SRE_FAST (0 << 2) 50*4882a593SmuzhiyunPAD_CTL_DSE_X1 (0 << 0) 51*4882a593SmuzhiyunPAD_CTL_DSE_X4 (1 << 0) 52*4882a593SmuzhiyunPAD_CTL_DSE_X2 (2 << 0) 53*4882a593SmuzhiyunPAD_CTL_DSE_X6 (3 << 0) 54*4882a593Smuzhiyun 55*4882a593SmuzhiyunExamples: 56*4882a593SmuzhiyunWhile iomuxc-lpsr is intended to be used by dedicated peripherals to take 57*4882a593Smuzhiyunadvantages of LPSR power mode, is also possible that an IP to use pads from 58*4882a593Smuzhiyunany of the iomux controllers. For example the I2C1 IP can use SCL pad from 59*4882a593Smuzhiyuniomuxc-lpsr controller and SDA pad from iomuxc controller as: 60*4882a593Smuzhiyun 61*4882a593Smuzhiyuni2c1: i2c@30a20000 { 62*4882a593Smuzhiyun pinctrl-names = "default"; 63*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c1_1 &pinctrl_i2c1_2>; 64*4882a593Smuzhiyun}; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyuniomuxc-lpsr@302c0000 { 67*4882a593Smuzhiyun compatible = "fsl,imx7d-iomuxc-lpsr"; 68*4882a593Smuzhiyun reg = <0x302c0000 0x10000>; 69*4882a593Smuzhiyun fsl,input-sel = <&iomuxc>; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun pinctrl_i2c1_1: i2c1grp-1 { 72*4882a593Smuzhiyun fsl,pins = < 73*4882a593Smuzhiyun MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f 74*4882a593Smuzhiyun >; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun}; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyuniomuxc@30330000 { 79*4882a593Smuzhiyun compatible = "fsl,imx7d-iomuxc"; 80*4882a593Smuzhiyun reg = <0x30330000 0x10000>; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun pinctrl_i2c1_2: i2c1grp-2 { 83*4882a593Smuzhiyun fsl,pins = < 84*4882a593Smuzhiyun MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f 85*4882a593Smuzhiyun >; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun}; 88