1*4882a593Smuzhiyun* Freescale i.MX6 UltraLite IOMUX Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunPlease refer to fsl,imx-pinctrl.txt in this directory for common binding part 4*4882a593Smuzhiyunand usage. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible: "fsl,imx6ul-iomuxc" for main IOMUX controller or 8*4882a593Smuzhiyun "fsl,imx6ull-iomuxc-snvs" for i.MX 6ULL's SNVS IOMUX controller. 9*4882a593Smuzhiyun- fsl,pins: each entry consists of 6 integers and represents the mux and config 10*4882a593Smuzhiyun setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val 11*4882a593Smuzhiyun input_val> are specified using a PIN_FUNC_ID macro, which can be found in 12*4882a593Smuzhiyun imx6ul-pinfunc.h under device tree source folder. The last integer CONFIG is 13*4882a593Smuzhiyun the pad setting value like pull-up on this pin. Please refer to i.MX6 UltraLite 14*4882a593Smuzhiyun Reference Manual for detailed CONFIG settings. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunCONFIG bits definition: 17*4882a593SmuzhiyunPAD_CTL_HYS (1 << 16) 18*4882a593SmuzhiyunPAD_CTL_PUS_100K_DOWN (0 << 14) 19*4882a593SmuzhiyunPAD_CTL_PUS_47K_UP (1 << 14) 20*4882a593SmuzhiyunPAD_CTL_PUS_100K_UP (2 << 14) 21*4882a593SmuzhiyunPAD_CTL_PUS_22K_UP (3 << 14) 22*4882a593SmuzhiyunPAD_CTL_PUE (1 << 13) 23*4882a593SmuzhiyunPAD_CTL_PKE (1 << 12) 24*4882a593SmuzhiyunPAD_CTL_ODE (1 << 11) 25*4882a593SmuzhiyunPAD_CTL_SPEED_LOW (0 << 6) 26*4882a593SmuzhiyunPAD_CTL_SPEED_MED (1 << 6) 27*4882a593SmuzhiyunPAD_CTL_SPEED_HIGH (3 << 6) 28*4882a593SmuzhiyunPAD_CTL_DSE_DISABLE (0 << 3) 29*4882a593SmuzhiyunPAD_CTL_DSE_260ohm (1 << 3) 30*4882a593SmuzhiyunPAD_CTL_DSE_130ohm (2 << 3) 31*4882a593SmuzhiyunPAD_CTL_DSE_87ohm (3 << 3) 32*4882a593SmuzhiyunPAD_CTL_DSE_65ohm (4 << 3) 33*4882a593SmuzhiyunPAD_CTL_DSE_52ohm (5 << 3) 34*4882a593SmuzhiyunPAD_CTL_DSE_43ohm (6 << 3) 35*4882a593SmuzhiyunPAD_CTL_DSE_37ohm (7 << 3) 36*4882a593SmuzhiyunPAD_CTL_SRE_FAST (1 << 0) 37*4882a593SmuzhiyunPAD_CTL_SRE_SLOW (0 << 0) 38