xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/cnxt,cx92755-pinctrl.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593SmuzhiyunConexant Digicolor CX92755 General Purpose Pin Mapping
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunThis document describes the device tree binding of the pin mapping hardware
4*4882a593Smuzhiyunmodules in the Conexant Digicolor CX92755 SoCs. The CX92755 in one of the
5*4882a593SmuzhiyunDigicolor series of SoCs.
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun=== Pin Controller Node ===
8*4882a593Smuzhiyun
9*4882a593SmuzhiyunRequired Properties:
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun- compatible: Must be "cnxt,cx92755-pinctrl"
12*4882a593Smuzhiyun- reg: Base address of the General Purpose Pin Mapping register block and the
13*4882a593Smuzhiyun  size of the block.
14*4882a593Smuzhiyun- gpio-controller: Marks the device node as a GPIO controller.
15*4882a593Smuzhiyun- #gpio-cells: Must be <2>. The first cell is the pin number and the
16*4882a593Smuzhiyun  second cell is used to specify flags. See include/dt-bindings/gpio/gpio.h
17*4882a593Smuzhiyun  for possible values.
18*4882a593Smuzhiyun
19*4882a593SmuzhiyunFor example, the following is the bare minimum node:
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun	pinctrl: pinctrl@f0000e20 {
22*4882a593Smuzhiyun		compatible = "cnxt,cx92755-pinctrl";
23*4882a593Smuzhiyun		reg = <0xf0000e20 0x100>;
24*4882a593Smuzhiyun		gpio-controller;
25*4882a593Smuzhiyun		#gpio-cells = <2>;
26*4882a593Smuzhiyun	};
27*4882a593Smuzhiyun
28*4882a593SmuzhiyunAs a pin controller device, in addition to the required properties, this node
29*4882a593Smuzhiyunshould also contain the pin configuration nodes that client devices reference,
30*4882a593Smuzhiyunif any.
31*4882a593Smuzhiyun
32*4882a593SmuzhiyunFor a general description of GPIO bindings, please refer to ../gpio/gpio.txt.
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun=== Pin Configuration Node ===
35*4882a593Smuzhiyun
36*4882a593SmuzhiyunEach pin configuration node is a sub-node of the pin controller node and is a
37*4882a593Smuzhiyuncontainer of an arbitrary number of subnodes, called pin group nodes in this
38*4882a593Smuzhiyundocument.
39*4882a593Smuzhiyun
40*4882a593SmuzhiyunPlease refer to the pinctrl-bindings.txt in this directory for details of the
41*4882a593Smuzhiyuncommon pinctrl bindings used by client devices, including the definition of a
42*4882a593Smuzhiyun"pin configuration node".
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun=== Pin Group Node ===
45*4882a593Smuzhiyun
46*4882a593SmuzhiyunA pin group node specifies the desired pin mux for an arbitrary number of
47*4882a593Smuzhiyunpins. The name of the pin group node is optional and not used.
48*4882a593Smuzhiyun
49*4882a593SmuzhiyunA pin group node only affects the properties specified in the node, and has no
50*4882a593Smuzhiyuneffect on any properties that are omitted.
51*4882a593Smuzhiyun
52*4882a593SmuzhiyunThe pin group node accepts a subset of the generic pin config properties. For
53*4882a593Smuzhiyundetails generic pin config properties, please refer to pinctrl-bindings.txt
54*4882a593Smuzhiyunand <include/linux/pinctrl/pinconfig-generic.h>.
55*4882a593Smuzhiyun
56*4882a593SmuzhiyunRequired Pin Group Node Properties:
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun- pins: Multiple strings. Specifies the name(s) of one or more pins to be
59*4882a593Smuzhiyun  configured by this node. The format of a pin name string is "GP_xy", where x
60*4882a593Smuzhiyun  is an uppercase character from 'A' to 'R', and y is a digit from 0 to 7.
61*4882a593Smuzhiyun- function: String. Specifies the pin mux selection. Values must be one of:
62*4882a593Smuzhiyun  "gpio", "client_a", "client_b", "client_c"
63*4882a593Smuzhiyun
64*4882a593SmuzhiyunExample:
65*4882a593Smuzhiyun	pinctrl: pinctrl@f0000e20 {
66*4882a593Smuzhiyun		compatible = "cnxt,cx92755-pinctrl";
67*4882a593Smuzhiyun		reg = <0xf0000e20 0x100>;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun		uart0_default: uart0_active {
70*4882a593Smuzhiyun			data_signals {
71*4882a593Smuzhiyun				pins = "GP_O0", "GP_O1";
72*4882a593Smuzhiyun				function = "client_b";
73*4882a593Smuzhiyun			};
74*4882a593Smuzhiyun		};
75*4882a593Smuzhiyun	};
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun	uart0: uart@f0000740 {
78*4882a593Smuzhiyun		compatible = "cnxt,cx92755-usart";
79*4882a593Smuzhiyun		...
80*4882a593Smuzhiyun		pinctrl-0 = <&uart0_default>;
81*4882a593Smuzhiyun		pinctrl-names = "default";
82*4882a593Smuzhiyun	};
83*4882a593Smuzhiyun
84*4882a593SmuzhiyunIn the example above, a single pin group configuration node defines the
85*4882a593Smuzhiyun"client select" for the Rx and Tx signals of uart0. The uart0 node references
86*4882a593Smuzhiyunthat pin configuration node using the &uart0_default phandle.
87