1*4882a593SmuzhiyunBroadcom Northstar plus (NSP) GPIO/PINCONF Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: 5*4882a593Smuzhiyun Must be "brcm,nsp-gpio-a" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun- reg: 8*4882a593Smuzhiyun Should contain the register physical address and length for each of 9*4882a593Smuzhiyun GPIO base, IO control registers 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun- #gpio-cells: 12*4882a593Smuzhiyun Must be two. The first cell is the GPIO pin number (within the 13*4882a593Smuzhiyun controller's pin space) and the second cell is used for the following: 14*4882a593Smuzhiyun bit[0]: polarity (0 for active high and 1 for active low) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun- gpio-controller: 17*4882a593Smuzhiyun Specifies that the node is a GPIO controller 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun- ngpios: 20*4882a593Smuzhiyun Number of gpios supported (58x25 supports 32 and 58x23 supports 24) 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunOptional properties: 23*4882a593Smuzhiyun- interrupts: 24*4882a593Smuzhiyun Interrupt ID 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun- interrupt-controller: 27*4882a593Smuzhiyun Specifies that the node is an interrupt controller 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun- gpio-ranges: 30*4882a593Smuzhiyun Specifies the mapping between gpio controller and pin-controllers pins. 31*4882a593Smuzhiyun This requires 4 fields in cells defined as - 32*4882a593Smuzhiyun 1. Phandle of pin-controller. 33*4882a593Smuzhiyun 2. GPIO base pin offset. 34*4882a593Smuzhiyun 3 Pin-control base pin offset. 35*4882a593Smuzhiyun 4. number of gpio pins which are linearly mapped from pin base. 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunSupported generic PINCONF properties in child nodes: 38*4882a593Smuzhiyun- pins: 39*4882a593Smuzhiyun The list of pins (within the controller's own pin space) that properties 40*4882a593Smuzhiyun in the node apply to. Pin names are "gpio-<pin>" 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun- bias-disable: 43*4882a593Smuzhiyun Disable pin bias 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun- bias-pull-up: 46*4882a593Smuzhiyun Enable internal pull up resistor 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun- bias-pull-down: 49*4882a593Smuzhiyun Enable internal pull down resistor 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun- drive-strength: 52*4882a593Smuzhiyun Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA) 53*4882a593Smuzhiyun 54*4882a593SmuzhiyunExample: 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun gpioa: gpio@18000020 { 57*4882a593Smuzhiyun compatible = "brcm,nsp-gpio-a"; 58*4882a593Smuzhiyun reg = <0x18000020 0x100>, 59*4882a593Smuzhiyun <0x1803f1c4 0x1c>; 60*4882a593Smuzhiyun #gpio-cells = <2>; 61*4882a593Smuzhiyun gpio-controller; 62*4882a593Smuzhiyun ngpios = <32>; 63*4882a593Smuzhiyun gpio-ranges = <&pinctrl 0 0 31>; 64*4882a593Smuzhiyun interrupt-controller; 65*4882a593Smuzhiyun interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* Hog a few default settings */ 68*4882a593Smuzhiyun pinctrl-names = "default"; 69*4882a593Smuzhiyun pinctrl-0 = <&led>; 70*4882a593Smuzhiyun led: led { 71*4882a593Smuzhiyun pins = "gpio-1"; 72*4882a593Smuzhiyun bias-pull-up; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun pwr: pwr { 76*4882a593Smuzhiyun gpio-hog; 77*4882a593Smuzhiyun gpios = <3 1>; 78*4882a593Smuzhiyun output-high; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun }; 81