1*4882a593SmuzhiyunBroadcom Northstar2 IOMUX Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Northstar2 IOMUX controller supports group based mux configuration. There 4*4882a593Smuzhiyunare some individual pins that support modifying the pinconf parameters. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- compatible: 9*4882a593Smuzhiyun Must be "brcm,ns2-pinmux" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun- reg: 12*4882a593Smuzhiyun Define the base and range of the I/O address space that contains the 13*4882a593Smuzhiyun Northstar2 IOMUX and pin configuration registers. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunProperties in sub nodes: 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun- function: 18*4882a593Smuzhiyun The mux function to select 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun- groups: 21*4882a593Smuzhiyun The list of groups to select with a given function 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun- pins: 24*4882a593Smuzhiyun List of pin names to change configuration 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunThe generic properties bias-disable, bias-pull-down, bias-pull-up, 27*4882a593Smuzhiyundrive-strength, slew-rate, input-enable, input-disable are supported 28*4882a593Smuzhiyunfor some individual pins listed at the end. 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunFor more details, refer to 31*4882a593SmuzhiyunDocumentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunFor example: 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun pinctrl: pinctrl@6501d130 { 36*4882a593Smuzhiyun compatible = "brcm,ns2-pinmux"; 37*4882a593Smuzhiyun reg = <0x6501d130 0x08>, 38*4882a593Smuzhiyun <0x660a0028 0x04>, 39*4882a593Smuzhiyun <0x660009b0 0x40>; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun pinctrl-names = "default"; 42*4882a593Smuzhiyun pinctrl-0 = <&nand_sel &uart3_rx &sdio0_d4>; 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Select nand function */ 45*4882a593Smuzhiyun nand_sel: nand_sel { 46*4882a593Smuzhiyun function = "nand"; 47*4882a593Smuzhiyun groups = "nand_grp"; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* Pull up the uart3 rx pin */ 51*4882a593Smuzhiyun uart3_rx: uart3_rx { 52*4882a593Smuzhiyun pins = "uart3_sin"; 53*4882a593Smuzhiyun bias-pull-up; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* Set the drive strength of sdio d4 pin */ 57*4882a593Smuzhiyun sdio0_d4: sdio0_d4 { 58*4882a593Smuzhiyun pins = "sdio0_data4"; 59*4882a593Smuzhiyun drive-strength = <8>; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun }; 62*4882a593Smuzhiyun 63*4882a593SmuzhiyunList of supported functions and groups in Northstar2: 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun"nand": "nand_grp" 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun"nor": "nor_data_grp", "nor_adv_grp", "nor_addr_0_3_grp", "nor_addr_4_5_grp", 68*4882a593Smuzhiyun "nor_addr_6_7_grp", "nor_addr_8_9_grp", "nor_addr_10_11_grp", 69*4882a593Smuzhiyun "nor_addr_12_15_grp" 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun"gpio": "gpio_0_1_grp", "gpio_2_5_grp", "gpio_6_7_grp", "gpio_8_9_grp", 72*4882a593Smuzhiyun "gpio_10_11_grp", "gpio_12_13_grp", "gpio_14_17_grp", "gpio_18_19_grp", 73*4882a593Smuzhiyun "gpio_20_21_grp", "gpio_22_23_grp", "gpio_24_25_grp", "gpio_26_27_grp", 74*4882a593Smuzhiyun "gpio_28_29_grp", "gpio_30_31_grp" 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun"pcie": "pcie_ab1_clk_wak_grp", "pcie_a3_clk_wak_grp", "pcie_b3_clk_wak_grp", 77*4882a593Smuzhiyun "pcie_b2_clk_wak_grp", "pcie_a2_clk_wak_grp" 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun"uart0": "uart0_modem_grp", "uart0_rts_cts_grp", "uart0_in_out_grp" 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun"uart1": "uart1_ext_clk_grp", "uart1_dcd_dsr_grp", "uart1_ri_dtr_grp", 82*4882a593Smuzhiyun "uart1_rts_cts_grp", "uart1_in_out_grp" 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun"uart2": "uart2_rts_cts_grp" 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun"pwm": "pwm_0_grp", "pwm_1_grp", "pwm_2_grp", "pwm_3_grp" 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun 89*4882a593SmuzhiyunList of pins that support pinconf parameters: 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun"qspi_wp", "qspi_hold", "qspi_cs", "qspi_sck", "uart3_sin", "uart3_sout", 92*4882a593Smuzhiyun"qspi_mosi", "qspi_miso", "spi0_fss", "spi0_rxd", "spi0_txd", "spi0_sck", 93*4882a593Smuzhiyun"spi1_fss", "spi1_rxd", "spi1_txd", "spi1_sck", "sdio0_data7", 94*4882a593Smuzhiyun"sdio0_emmc_rst", "sdio0_led_on", "sdio0_wp", "sdio0_data3", "sdio0_data4", 95*4882a593Smuzhiyun"sdio0_data5", "sdio0_data6", "sdio0_cmd", "sdio0_data0", "sdio0_data1", 96*4882a593Smuzhiyun"sdio0_data2", "sdio1_led_on", "sdio1_wp", "sdio0_cd_l", "sdio0_clk", 97*4882a593Smuzhiyun"sdio1_data5", "sdio1_data6", "sdio1_data7", "sdio1_emmc_rst", "sdio1_data1", 98*4882a593Smuzhiyun"sdio1_data2", "sdio1_data3", "sdio1_data4", "sdio1_cd_l", "sdio1_clk", 99*4882a593Smuzhiyun"sdio1_cmd", "sdio1_data0", "ext_mdio_0", "ext_mdc_0", "usb3_p1_vbus_ppc", 100*4882a593Smuzhiyun"usb3_p1_overcurrent", "usb3_p0_vbus_ppc", "usb3_p0_overcurrent", 101*4882a593Smuzhiyun"usb2_presence_indication", "usb2_vbus_present", "usb2_vbus_ppc", 102*4882a593Smuzhiyun"usb2_overcurrent", "sata_led1", "sata_led0" 103