1*4882a593SmuzhiyunBroadcom iProc GPIO/PINCONF Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible: 6*4882a593Smuzhiyun "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that 7*4882a593Smuzhiyun supports full-featured pinctrl and GPIO functions used in various iProc 8*4882a593Smuzhiyun based SoCs 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun May contain an SoC-specific compatibility string to accommodate any 11*4882a593Smuzhiyun SoC-specific features 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or 14*4882a593Smuzhiyun "brcm,cygnus-crmu-gpio" for Cygnus SoCs 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support 17*4882a593Smuzhiyun disabled 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general 20*4882a593Smuzhiyun pinctrl support completely disabled in this IP block. In Stingray, a 21*4882a593Smuzhiyun different IP block is used to handle pinctrl related functions 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun- reg: 24*4882a593Smuzhiyun Define the base and range of the I/O address space that contains SoC 25*4882a593SmuzhiyunGPIO/PINCONF controller registers 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun- ngpios: 28*4882a593Smuzhiyun Total number of in-use slots in GPIO controller 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun- #gpio-cells: 31*4882a593Smuzhiyun Must be two. The first cell is the GPIO pin number (within the 32*4882a593Smuzhiyuncontroller's pin space) and the second cell is used for the following: 33*4882a593Smuzhiyun bit[0]: polarity (0 for active high and 1 for active low) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun- gpio-controller: 36*4882a593Smuzhiyun Specifies that the node is a GPIO controller 37*4882a593Smuzhiyun 38*4882a593SmuzhiyunOptional properties: 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun- interrupts: 41*4882a593Smuzhiyun Interrupt ID 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun- interrupt-controller: 44*4882a593Smuzhiyun Specifies that the node is an interrupt controller 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun- gpio-ranges: 47*4882a593Smuzhiyun Specifies the mapping between gpio controller and pin-controllers pins. 48*4882a593Smuzhiyun This requires 4 fields in cells defined as - 49*4882a593Smuzhiyun 1. Phandle of pin-controller. 50*4882a593Smuzhiyun 2. GPIO base pin offset. 51*4882a593Smuzhiyun 3 Pin-control base pin offset. 52*4882a593Smuzhiyun 4. number of gpio pins which are linearly mapped from pin base. 53*4882a593Smuzhiyun 54*4882a593SmuzhiyunSupported generic PINCONF properties in child nodes: 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun- pins: 57*4882a593Smuzhiyun The list of pins (within the controller's own pin space) that properties 58*4882a593Smuzhiyunin the node apply to. Pin names are "gpio-<pin>" 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun- bias-disable: 61*4882a593Smuzhiyun Disable pin bias 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun- bias-pull-up: 64*4882a593Smuzhiyun Enable internal pull up resistor 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun- bias-pull-down: 67*4882a593Smuzhiyun Enable internal pull down resistor 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun- drive-strength: 70*4882a593Smuzhiyun Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA) 71*4882a593Smuzhiyun 72*4882a593SmuzhiyunExample: 73*4882a593Smuzhiyun gpio_ccm: gpio@1800a000 { 74*4882a593Smuzhiyun compatible = "brcm,cygnus-ccm-gpio"; 75*4882a593Smuzhiyun reg = <0x1800a000 0x50>, 76*4882a593Smuzhiyun <0x0301d164 0x20>; 77*4882a593Smuzhiyun ngpios = <24>; 78*4882a593Smuzhiyun #gpio-cells = <2>; 79*4882a593Smuzhiyun gpio-controller; 80*4882a593Smuzhiyun interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 81*4882a593Smuzhiyun interrupt-controller; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun touch_pins: touch_pins { 84*4882a593Smuzhiyun pwr: pwr { 85*4882a593Smuzhiyun pins = "gpio-0"; 86*4882a593Smuzhiyun drive-strength = <16>; 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun event: event { 90*4882a593Smuzhiyun pins = "gpio-1"; 91*4882a593Smuzhiyun bias-pull-up; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun gpio_asiu: gpio@180a5000 { 97*4882a593Smuzhiyun compatible = "brcm,cygnus-asiu-gpio"; 98*4882a593Smuzhiyun reg = <0x180a5000 0x668>; 99*4882a593Smuzhiyun ngpios = <146>; 100*4882a593Smuzhiyun #gpio-cells = <2>; 101*4882a593Smuzhiyun gpio-controller; 102*4882a593Smuzhiyun interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 103*4882a593Smuzhiyun interrupt-controller; 104*4882a593Smuzhiyun gpio-ranges = <&pinctrl 0 42 1>, 105*4882a593Smuzhiyun <&pinctrl 1 44 3>; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* 109*4882a593Smuzhiyun * Touchscreen that uses the CCM GPIO 0 and 1 110*4882a593Smuzhiyun */ 111*4882a593Smuzhiyun tsc { 112*4882a593Smuzhiyun ... 113*4882a593Smuzhiyun ... 114*4882a593Smuzhiyun gpio-pwr = <&gpio_ccm 0 0>; 115*4882a593Smuzhiyun gpio-event = <&gpio_ccm 1 0>; 116*4882a593Smuzhiyun }; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /* Bluetooth that uses the ASIU GPIO 5, with polarity inverted */ 119*4882a593Smuzhiyun bluetooth { 120*4882a593Smuzhiyun ... 121*4882a593Smuzhiyun ... 122*4882a593Smuzhiyun bcm,rfkill-bank-sel = <&gpio_asiu 5 1> 123*4882a593Smuzhiyun } 124