1*4882a593SmuzhiyunBroadcom Cygnus IOMUX Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Cygnus IOMUX controller supports group based mux configuration. In 4*4882a593Smuzhiyunaddition, certain pins can be muxed to GPIO function individually. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- compatible: 9*4882a593Smuzhiyun Must be "brcm,cygnus-pinmux" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun- reg: 12*4882a593Smuzhiyun Define the base and range of the I/O address space that contains the Cygnus 13*4882a593SmuzhiyunIOMUX registers 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunProperties in subnodes: 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun- function: 18*4882a593Smuzhiyun The mux function to select 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun- groups: 21*4882a593Smuzhiyun The list of groups to select with a given function 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunFor more details, refer to 24*4882a593SmuzhiyunDocumentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunFor example: 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun pinmux: pinmux@0301d0c8 { 29*4882a593Smuzhiyun compatible = "brcm,cygnus-pinmux"; 30*4882a593Smuzhiyun reg = <0x0301d0c8 0x1b0>; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun pinctrl-names = "default"; 33*4882a593Smuzhiyun pinctrl-0 = <&i2s0_default>; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun i2s0_default: i2s0_default { 36*4882a593Smuzhiyun mux { 37*4882a593Smuzhiyun function = "i2s0"; 38*4882a593Smuzhiyun groups = "i2s0_0_grp", "i2s0_1_grp"; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunList of supported functions and groups in Cygnus: 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun"i2s0": "i2s0_0_grp", "i2s0_1_grp" 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun"i2s1": "i2s1_0_grp", "i2s1_1_grp" 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun"i2s2": "i2s2_0_grp", "i2s2_1_grp", "i2s2_2_grp", "i2s2_3_grp", "i2s2_4_grp" 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun"spdif": "spdif_grp" 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun"pwm0": "pwm0_grp" 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun"pwm1": "pwm1_grp" 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun"pwm2": "pwm2_grp" 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun"pwm3": "pwm3_grp" 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun"pwm4": "pwm4_grp" 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun"pwm5": "pwm5_grp" 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun"key": "key0_grp", "key1_grp", "key2_grp", "key3_grp", "key4_grp", "key5_grp", 66*4882a593Smuzhiyun"key6_grp", "key7_grp", "key8_grp", "key9_grp", "key10_grp", "key11_grp", 67*4882a593Smuzhiyun"key12_grp", "key13_grp", "key14_grp", "key15_grp" 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun"audio_dte": "audio_dte0_grp", "audio_dte1_grp", "audio_dte2_grp", "audio_dte3_grp" 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun"smart_card0": "smart_card0_grp", "smart_card0_fcb_grp" 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun"smart_card1": "smart_card1_grp", "smart_card1_fcb_grp" 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun"spi0": "spi0_grp" 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun"spi1": "spi1_grp" 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun"spi2": "spi2_grp" 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun"spi3": "spi3_grp" 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun"spi4": "spi4_0_grp", "spi4_1_grp" 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun"spi5": "spi5_grp" 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun"sw_led0": "sw_led0_0_grp", "sw_led0_1_grp" 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun"sw_led1": "sw_led1_grp" 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun"sw_led2": "sw_led2_0_grp", "sw_led2_1_grp" 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun"d1w": "d1w_grp" 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun"lcd": "lcd_grp" 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun"sram": "sram_0_grp", "sram_1_grp" 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun"uart0": "uart0_grp" 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun"uart1": "uart1_grp", "uart1_dte_grp" 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun"uart2": "uart2_grp" 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun"uart3": "uart3_grp" 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun"uart4": "uart4_grp" 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun"qspi": "qspi_0_grp", "qspi_1_grp" 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun"nand": "nand_grp" 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun"sdio0": "sdio0_grp", "sdio0_cd_grp", "sdio0_mmc_grp" 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun"sdio1": "sdio1_data_0_grp", "sdio1_data_1_grp", "sdio1_cd_grp", 116*4882a593Smuzhiyun"sdio1_led_grp", "sdio1_mmc_grp" 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun"can0": "can0_grp" 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun"can1": "can1_grp" 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun"cam": "cam_led_grp", "cam_0_grp", "cam_1_grp" 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun"bsc1": "bsc1_grp" 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun"pcie_clkreq": "pcie_clkreq_grp" 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun"usb0_oc": "usb0_oc_grp" 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun"usb1_oc": "usb1_oc_grp" 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun"usb2_oc": "usb2_oc_grp" 133