xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/brcm,nsp-pinmux.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593SmuzhiyunBroadcom NSP (Northstar plus) IOMUX Controller
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunThe NSP IOMUX controller supports group based mux configuration. In
4*4882a593Smuzhiyunaddition, certain pins can be muxed to GPIO function individually.
5*4882a593Smuzhiyun
6*4882a593SmuzhiyunRequired properties:
7*4882a593Smuzhiyun- compatible:
8*4882a593Smuzhiyun    Must be "brcm,nsp-pinmux"
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun- reg:
11*4882a593Smuzhiyun    Should contain the register physical address and length for each of
12*4882a593Smuzhiyun    GPIO_CONTROL0, GP_AUX_SEL and IPROC_CONFIG IOMUX registers
13*4882a593Smuzhiyun
14*4882a593SmuzhiyunProperties in subnodes:
15*4882a593Smuzhiyun- function:
16*4882a593Smuzhiyun    The mux function to select
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun- groups:
19*4882a593Smuzhiyun    The list of groups to select with a given function
20*4882a593Smuzhiyun
21*4882a593SmuzhiyunFor more details, refer to
22*4882a593SmuzhiyunDocumentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
23*4882a593Smuzhiyun
24*4882a593SmuzhiyunFor example:
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun	pinmux: pinmux@1803f1c0 {
27*4882a593Smuzhiyun		compatible = "brcm,nsp-pinmux";
28*4882a593Smuzhiyun		reg = <0x1803f1c0 0x04>,
29*4882a593Smuzhiyun		      <0x18030028 0x04>,
30*4882a593Smuzhiyun		      <0x1803f408 0x04>;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun		pinctrl-names = "default";
33*4882a593Smuzhiyun		pinctrl-0 = <&pwm &gpio_b &nand_sel>;
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun		pwm: pwm {
36*4882a593Smuzhiyun			function = "pwm";
37*4882a593Smuzhiyun			groups = "pwm0_grp", "pwm1_grp";
38*4882a593Smuzhiyun		};
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun		gpio_b: gpio_b {
41*4882a593Smuzhiyun			function = "gpio_b";
42*4882a593Smuzhiyun			groups = "gpio_b_0_grp", "gpio_b_1_grp";
43*4882a593Smuzhiyun		};
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun		nand_sel: nand_sel {
46*4882a593Smuzhiyun			function = "nand";
47*4882a593Smuzhiyun			groups = "nand_grp";
48*4882a593Smuzhiyun		};
49*4882a593Smuzhiyun	};
50*4882a593Smuzhiyun
51*4882a593SmuzhiyunList of supported functions and groups in Northstar Plus:
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun"spi": "spi_grp"
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun"i2c": "i2c_grp"
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun"mdio": "mdio_grp"
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun"pwm": "pwm0_grp", "pwm1_grp", "pwm2_grp", "pwm3_grp"
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun"gpio_b": "gpio_b_0_grp", "gpio_b_1_grp", "gpio_b_2_grp", "gpio_b_3_grp"
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun"uart1": "uart1_grp"
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun"uart2": "uart2_grp"
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun"synce": "synce_grp"
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun"sata_led_grps": "sata0_led_grp", "sata1_led_grp"
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun"xtal_out": "xtal_out_grp"
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun"sdio": "sdio_pwr_grp", "sdio_1p8v_grp"
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun"switch_led": "switch_p05_led0_grp", "switch_p05_led1_grp"
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun"nand": "nand_grp"
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun"emmc": "emmc_grp"
80