1*4882a593SmuzhiyunAxis ARTPEC-6 Pin Controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: "axis,artpec6-pinctrl". 5*4882a593Smuzhiyun- reg: Should contain the register physical address and length for the pin 6*4882a593Smuzhiyun controller. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunA pinctrl node should contain at least one subnode representing the pinctrl 9*4882a593Smuzhiyungroups available on the machine. Each subnode will list the mux function 10*4882a593Smuzhiyunrequired and what pin group it will use. Each subnode will also configure the 11*4882a593Smuzhiyundrive strength and bias pullup of the pin group. If either of these options is 12*4882a593Smuzhiyunnot set, its actual value will be unspecified. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunRequired subnode-properties: 16*4882a593Smuzhiyun- function: Function to mux. 17*4882a593Smuzhiyun- groups: Name of the pin group to use for the function above. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun Available functions and groups (function: group0, group1...): 20*4882a593Smuzhiyun gpio: cpuclkoutgrp0, udlclkoutgrp0, i2c1grp0, i2c2grp0, 21*4882a593Smuzhiyun i2c3grp0, i2s0grp0, i2s1grp0, i2srefclkgrp0, spi0grp0, 22*4882a593Smuzhiyun spi1grp0, pciedebuggrp0, uart0grp0, uart0grp1, uart0grp2, 23*4882a593Smuzhiyun uart1grp0, uart1grp1, uart2grp0, uart2grp1, uart2grp2, 24*4882a593Smuzhiyun uart3grp0, uart4grp0, uart4grp1, uart5grp0, uart5grp1, 25*4882a593Smuzhiyun uart5nocts 26*4882a593Smuzhiyun cpuclkout: cpuclkoutgrp0 27*4882a593Smuzhiyun udlclkout: udlclkoutgrp0 28*4882a593Smuzhiyun i2c1: i2c1grp0 29*4882a593Smuzhiyun i2c2: i2c2grp0 30*4882a593Smuzhiyun i2c3: i2c3grp0 31*4882a593Smuzhiyun i2s0: i2s0grp0 32*4882a593Smuzhiyun i2s1: i2s1grp0 33*4882a593Smuzhiyun i2srefclk: i2srefclkgrp0 34*4882a593Smuzhiyun spi0: spi0grp0 35*4882a593Smuzhiyun spi1: spi1grp0 36*4882a593Smuzhiyun pciedebug: pciedebuggrp0 37*4882a593Smuzhiyun uart0: uart0grp0, uart0grp1, uart0grp2 38*4882a593Smuzhiyun uart1: uart1grp0, uart1grp1 39*4882a593Smuzhiyun uart2: uart2grp0, uart2grp1, uart2grp2 40*4882a593Smuzhiyun uart3: uart3grp0 41*4882a593Smuzhiyun uart4: uart4grp0, uart4grp1 42*4882a593Smuzhiyun uart5: uart5grp0, uart5grp1, uart5nocts 43*4882a593Smuzhiyun nand: nandgrp0 44*4882a593Smuzhiyun sdio0: sdio0grp0 45*4882a593Smuzhiyun sdio1: sdio1grp0 46*4882a593Smuzhiyun ethernet: ethernetgrp0 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun 49*4882a593SmuzhiyunOptional subnode-properties (see pinctrl-bindings.txt): 50*4882a593Smuzhiyun- drive-strength: 4, 6, 8, 9 mA. For SD and NAND pins, this is for 3.3V VCCQ3. 51*4882a593Smuzhiyun- bias-pull-up 52*4882a593Smuzhiyun- bias-disable 53*4882a593Smuzhiyun 54*4882a593SmuzhiyunExamples: 55*4882a593Smuzhiyunpinctrl@f801d000 { 56*4882a593Smuzhiyun compatible = "axis,artpec6-pinctrl"; 57*4882a593Smuzhiyun reg = <0xf801d000 0x400>; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun pinctrl_uart0: uart0grp { 60*4882a593Smuzhiyun function = "uart0"; 61*4882a593Smuzhiyun groups = "uart0grp0"; 62*4882a593Smuzhiyun drive-strength = <4>; 63*4882a593Smuzhiyun bias-pull-up; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun pinctrl_uart3: uart3grp { 66*4882a593Smuzhiyun function = "uart3"; 67*4882a593Smuzhiyun groups = "uart3grp0"; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun}; 70*4882a593Smuzhiyunuart0: uart@f8036000 { 71*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 72*4882a593Smuzhiyun reg = <0xf8036000 0x1000>; 73*4882a593Smuzhiyun interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>; 74*4882a593Smuzhiyun clocks = <&pll2div24>, <&apb_pclk>; 75*4882a593Smuzhiyun clock-names = "uart_clk", "apb_pclk"; 76*4882a593Smuzhiyun pinctrl-names = "default"; 77*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart0>; 78*4882a593Smuzhiyun}; 79*4882a593Smuzhiyunuart3: uart@f8039000 { 80*4882a593Smuzhiyun compatible = "arm,pl011", "arm,primecell"; 81*4882a593Smuzhiyun reg = <0xf8039000 0x1000>; 82*4882a593Smuzhiyun interrupts = <0 128 IRQ_TYPE_LEVEL_HIGH>; 83*4882a593Smuzhiyun clocks = <&pll2div24>, <&apb_pclk>; 84*4882a593Smuzhiyun clock-names = "uart_clk", "apb_pclk"; 85*4882a593Smuzhiyun pinctrl-names = "default"; 86*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_uart3>; 87*4882a593Smuzhiyun}; 88