xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/pinctrl/atmel,at91-pio4-pinctrl.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun* Atmel PIO4 Controller
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunThe Atmel PIO4 controller is used to select the function of a pin and to
4*4882a593Smuzhiyunconfigure it.
5*4882a593Smuzhiyun
6*4882a593SmuzhiyunRequired properties:
7*4882a593Smuzhiyun- compatible:
8*4882a593Smuzhiyun	"atmel,sama5d2-pinctrl"
9*4882a593Smuzhiyun	"microchip,sama7g5-pinctrl"
10*4882a593Smuzhiyun- reg: base address and length of the PIO controller.
11*4882a593Smuzhiyun- interrupts: interrupt outputs from the controller, one for each bank.
12*4882a593Smuzhiyun- interrupt-controller: mark the device node as an interrupt controller.
13*4882a593Smuzhiyun- #interrupt-cells: should be two.
14*4882a593Smuzhiyun- gpio-controller: mark the device node as a gpio controller.
15*4882a593Smuzhiyun- #gpio-cells: should be two.
16*4882a593Smuzhiyun
17*4882a593SmuzhiyunPlease refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
18*4882a593Smuzhiyuna general description of GPIO and interrupt bindings.
19*4882a593Smuzhiyun
20*4882a593SmuzhiyunPlease refer to pinctrl-bindings.txt in this directory for details of the
21*4882a593Smuzhiyuncommon pinctrl bindings used by client devices.
22*4882a593Smuzhiyun
23*4882a593SmuzhiyunSubnode format
24*4882a593SmuzhiyunEach node (or subnode) will list the pins it needs and how to configured these
25*4882a593Smuzhiyunpins.
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun	node {
28*4882a593Smuzhiyun		pinmux = <PIN_NUMBER_PINMUX>;
29*4882a593Smuzhiyun		GENERIC_PINCONFIG;
30*4882a593Smuzhiyun	};
31*4882a593Smuzhiyun
32*4882a593SmuzhiyunRequired properties:
33*4882a593Smuzhiyun- pinmux: integer array. Each integer represents a pin number plus mux and
34*4882a593Smuzhiyunioset settings. Use the macros from boot/dts/<soc>-pinfunc.h file to get the
35*4882a593Smuzhiyunright representation of the pin.
36*4882a593Smuzhiyun
37*4882a593SmuzhiyunOptional properties:
38*4882a593Smuzhiyun- GENERIC_PINCONFIG: generic pinconfig options to use, bias-disable,
39*4882a593Smuzhiyunbias-pull-down, bias-pull-up, drive-open-drain, input-schmitt-enable,
40*4882a593Smuzhiyuninput-debounce, output-low, output-high.
41*4882a593Smuzhiyun- atmel,drive-strength: 0 or 1 for low drive, 2 for medium drive and 3 for
42*4882a593Smuzhiyunhigh drive. The default value is low drive.
43*4882a593Smuzhiyun
44*4882a593SmuzhiyunExample:
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun#include <sama5d2-pinfunc.h>
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun...
49*4882a593Smuzhiyun{
50*4882a593Smuzhiyun	pioA: pinctrl@fc038000 {
51*4882a593Smuzhiyun		compatible = "atmel,sama5d2-pinctrl";
52*4882a593Smuzhiyun		reg = <0xfc038000 0x600>;
53*4882a593Smuzhiyun		interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
54*4882a593Smuzhiyun			     <68 IRQ_TYPE_LEVEL_HIGH 7>,
55*4882a593Smuzhiyun			     <69 IRQ_TYPE_LEVEL_HIGH 7>,
56*4882a593Smuzhiyun			     <70 IRQ_TYPE_LEVEL_HIGH 7>;
57*4882a593Smuzhiyun		interrupt-controller;
58*4882a593Smuzhiyun		#interrupt-cells = <2>;
59*4882a593Smuzhiyun		gpio-controller;
60*4882a593Smuzhiyun		#gpio-cells = <2>;
61*4882a593Smuzhiyun		clocks = <&pioA_clk>;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun		pinctrl_i2c0_default: i2c0_default {
64*4882a593Smuzhiyun			pinmux = <PIN_PD21__TWD0>,
65*4882a593Smuzhiyun				 <PIN_PD22__TWCK0>;
66*4882a593Smuzhiyun			bias-disable;
67*4882a593Smuzhiyun		};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun		pinctrl_led_gpio_default: led_gpio_default {
70*4882a593Smuzhiyun			pinmux = <PIN_PB0>,
71*4882a593Smuzhiyun				 <PIN_PB5>;
72*4882a593Smuzhiyun			bias-pull-up;
73*4882a593Smuzhiyun			atmel,drive-strength = <ATMEL_PIO_DRVSTR_ME>;
74*4882a593Smuzhiyun		};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun		pinctrl_sdmmc1_default: sdmmc1_default {
77*4882a593Smuzhiyun			cmd_data {
78*4882a593Smuzhiyun				pinmux = <PIN_PA28__SDMMC1_CMD>,
79*4882a593Smuzhiyun					 <PIN_PA18__SDMMC1_DAT0>,
80*4882a593Smuzhiyun					 <PIN_PA19__SDMMC1_DAT1>,
81*4882a593Smuzhiyun					 <PIN_PA20__SDMMC1_DAT2>,
82*4882a593Smuzhiyun					 <PIN_PA21__SDMMC1_DAT3>;
83*4882a593Smuzhiyun				bias-pull-up;
84*4882a593Smuzhiyun			};
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun			ck_cd {
87*4882a593Smuzhiyun				pinmux = <PIN_PA22__SDMMC1_CK>,
88*4882a593Smuzhiyun					 <PIN_PA30__SDMMC1_CD>;
89*4882a593Smuzhiyun				bias-disable;
90*4882a593Smuzhiyun			};
91*4882a593Smuzhiyun		};
92*4882a593Smuzhiyun		...
93*4882a593Smuzhiyun	};
94*4882a593Smuzhiyun};
95*4882a593Smuzhiyun...
96