1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-or-later 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2400-pinctrl.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: ASPEED AST2400 Pin Controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Andrew Jeffery <andrew@aj.id.au> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: |+ 13*4882a593Smuzhiyun The pin controller node should be the child of a syscon node with the 14*4882a593Smuzhiyun required property: 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun - compatible: Should be one of the following: 17*4882a593Smuzhiyun "aspeed,ast2400-scu", "syscon", "simple-mfd" 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun Refer to the the bindings described in 20*4882a593Smuzhiyun Documentation/devicetree/bindings/mfd/syscon.yaml 21*4882a593Smuzhiyun 22*4882a593Smuzhiyunproperties: 23*4882a593Smuzhiyun compatible: 24*4882a593Smuzhiyun const: aspeed,ast2400-pinctrl 25*4882a593Smuzhiyun reg: 26*4882a593Smuzhiyun description: | 27*4882a593Smuzhiyun A hint for the memory regions associated with the pin-controller 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunpatternProperties: 30*4882a593Smuzhiyun '^.*$': 31*4882a593Smuzhiyun if: 32*4882a593Smuzhiyun type: object 33*4882a593Smuzhiyun then: 34*4882a593Smuzhiyun patternProperties: 35*4882a593Smuzhiyun "^function|groups$": 36*4882a593Smuzhiyun $ref: "/schemas/types.yaml#/definitions/string" 37*4882a593Smuzhiyun enum: [ ACPI, ADC0, ADC1, ADC10, ADC11, ADC12, ADC13, ADC14, ADC15, 38*4882a593Smuzhiyun ADC2, ADC3, ADC4, ADC5, ADC6, ADC7, ADC8, ADC9, BMCINT, DDCCLK, DDCDAT, 39*4882a593Smuzhiyun EXTRST, FLACK, FLBUSY, FLWP, GPID, GPID0, GPID2, GPID4, GPID6, GPIE0, 40*4882a593Smuzhiyun GPIE2, GPIE4, GPIE6, I2C10, I2C11, I2C12, I2C13, I2C14, I2C3, I2C4, 41*4882a593Smuzhiyun I2C5, I2C6, I2C7, I2C8, I2C9, LPCPD, LPCPME, LPCRST, LPCSMI, MAC1LINK, 42*4882a593Smuzhiyun MAC2LINK, MDIO1, MDIO2, NCTS1, NCTS2, NCTS3, NCTS4, NDCD1, NDCD2, 43*4882a593Smuzhiyun NDCD3, NDCD4, NDSR1, NDSR2, NDSR3, NDSR4, NDTR1, NDTR2, NDTR3, NDTR4, 44*4882a593Smuzhiyun NDTS4, NRI1, NRI2, NRI3, NRI4, NRTS1, NRTS2, NRTS3, OSCCLK, PWM0, 45*4882a593Smuzhiyun PWM1, PWM2, PWM3, PWM4, PWM5, PWM6, PWM7, RGMII1, RGMII2, RMII1, 46*4882a593Smuzhiyun RMII2, ROM16, ROM8, ROMCS1, ROMCS2, ROMCS3, ROMCS4, RXD1, RXD2, RXD3, 47*4882a593Smuzhiyun RXD4, SALT1, SALT2, SALT3, SALT4, SD1, SD2, SGPMCK, SGPMI, SGPMLD, 48*4882a593Smuzhiyun SGPMO, SGPSCK, SGPSI0, SGPSI1, SGPSLD, SIOONCTRL, SIOPBI, SIOPBO, 49*4882a593Smuzhiyun SIOPWREQ, SIOPWRGD, SIOS3, SIOS5, SIOSCI, SPI1, SPI1DEBUG, SPI1PASSTHRU, 50*4882a593Smuzhiyun SPICS1, TIMER3, TIMER4, TIMER5, TIMER6, TIMER7, TIMER8, TXD1, TXD2, 51*4882a593Smuzhiyun TXD3, TXD4, UART6, USB11D1, USB11H2, USB2D1, USB2H1, USBCKI, VGABIOS_ROM, 52*4882a593Smuzhiyun VGAHS, VGAVS, VPI18, VPI24, VPI30, VPO12, VPO24, WDTRST1, WDTRST2] 53*4882a593Smuzhiyun 54*4882a593Smuzhiyunrequired: 55*4882a593Smuzhiyun - compatible 56*4882a593Smuzhiyun 57*4882a593SmuzhiyunadditionalProperties: false 58*4882a593Smuzhiyun 59*4882a593Smuzhiyunexamples: 60*4882a593Smuzhiyun - | 61*4882a593Smuzhiyun syscon: scu@1e6e2000 { 62*4882a593Smuzhiyun compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; 63*4882a593Smuzhiyun reg = <0x1e6e2000 0x1a8>; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun pinctrl: pinctrl { 66*4882a593Smuzhiyun compatible = "aspeed,g4-pinctrl"; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun pinctrl_i2c3_default: i2c3_default { 69*4882a593Smuzhiyun function = "I2C3"; 70*4882a593Smuzhiyun groups = "I2C3"; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun pinctrl_gpioh0_unbiased_default: gpioh0 { 74*4882a593Smuzhiyun pins = "A8"; 75*4882a593Smuzhiyun bias-disable; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun }; 79