1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/pinctrl/allwinner,sun4i-a10-pinctrl.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Allwinner A10 Pin Controller Device Tree Bindings
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Chen-Yu Tsai <wens@csie.org>
11*4882a593Smuzhiyun  - Maxime Ripard <mripard@kernel.org>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyunproperties:
14*4882a593Smuzhiyun  "#gpio-cells":
15*4882a593Smuzhiyun    const: 3
16*4882a593Smuzhiyun    description:
17*4882a593Smuzhiyun      GPIO consumers must use three arguments, first the number of the
18*4882a593Smuzhiyun      bank, then the pin number inside that bank, and finally the GPIO
19*4882a593Smuzhiyun      flags.
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun  "#interrupt-cells":
22*4882a593Smuzhiyun    const: 3
23*4882a593Smuzhiyun    description:
24*4882a593Smuzhiyun      Interrupts consumers must use three arguments, first the number
25*4882a593Smuzhiyun      of the bank, then the pin number inside that bank, and finally
26*4882a593Smuzhiyun      the interrupts flags.
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun  compatible:
29*4882a593Smuzhiyun    enum:
30*4882a593Smuzhiyun      - allwinner,sun4i-a10-pinctrl
31*4882a593Smuzhiyun      - allwinner,sun5i-a10s-pinctrl
32*4882a593Smuzhiyun      - allwinner,sun5i-a13-pinctrl
33*4882a593Smuzhiyun      - allwinner,sun6i-a31-pinctrl
34*4882a593Smuzhiyun      - allwinner,sun6i-a31-r-pinctrl
35*4882a593Smuzhiyun      - allwinner,sun6i-a31s-pinctrl
36*4882a593Smuzhiyun      - allwinner,sun7i-a20-pinctrl
37*4882a593Smuzhiyun      - allwinner,sun8i-a23-pinctrl
38*4882a593Smuzhiyun      - allwinner,sun8i-a23-r-pinctrl
39*4882a593Smuzhiyun      - allwinner,sun8i-a33-pinctrl
40*4882a593Smuzhiyun      - allwinner,sun8i-a83t-pinctrl
41*4882a593Smuzhiyun      - allwinner,sun8i-a83t-r-pinctrl
42*4882a593Smuzhiyun      - allwinner,sun8i-h3-pinctrl
43*4882a593Smuzhiyun      - allwinner,sun8i-h3-r-pinctrl
44*4882a593Smuzhiyun      - allwinner,sun8i-r40-pinctrl
45*4882a593Smuzhiyun      - allwinner,sun8i-v3-pinctrl
46*4882a593Smuzhiyun      - allwinner,sun8i-v3s-pinctrl
47*4882a593Smuzhiyun      - allwinner,sun9i-a80-pinctrl
48*4882a593Smuzhiyun      - allwinner,sun9i-a80-r-pinctrl
49*4882a593Smuzhiyun      - allwinner,sun50i-a64-pinctrl
50*4882a593Smuzhiyun      - allwinner,sun50i-a64-r-pinctrl
51*4882a593Smuzhiyun      - allwinner,sun50i-a100-pinctrl
52*4882a593Smuzhiyun      - allwinner,sun50i-a100-r-pinctrl
53*4882a593Smuzhiyun      - allwinner,sun50i-h5-pinctrl
54*4882a593Smuzhiyun      - allwinner,sun50i-h6-pinctrl
55*4882a593Smuzhiyun      - allwinner,sun50i-h6-r-pinctrl
56*4882a593Smuzhiyun      - allwinner,suniv-f1c100s-pinctrl
57*4882a593Smuzhiyun      - nextthing,gr8-pinctrl
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun  reg:
60*4882a593Smuzhiyun    maxItems: 1
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun  interrupts:
63*4882a593Smuzhiyun    minItems: 1
64*4882a593Smuzhiyun    maxItems: 7
65*4882a593Smuzhiyun    description:
66*4882a593Smuzhiyun      One interrupt per external interrupt bank supported on the
67*4882a593Smuzhiyun      controller, sorted by bank number ascending order.
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun  clocks:
70*4882a593Smuzhiyun    items:
71*4882a593Smuzhiyun      - description: Bus Clock
72*4882a593Smuzhiyun      - description: High Frequency Oscillator
73*4882a593Smuzhiyun      - description: Low Frequency Oscillator
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun  clock-names:
76*4882a593Smuzhiyun    items:
77*4882a593Smuzhiyun      - const: apb
78*4882a593Smuzhiyun      - const: hosc
79*4882a593Smuzhiyun      - const: losc
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun  resets:
82*4882a593Smuzhiyun    maxItems: 1
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun  gpio-controller: true
85*4882a593Smuzhiyun  interrupt-controller: true
86*4882a593Smuzhiyun  gpio-line-names: true
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun  input-debounce:
89*4882a593Smuzhiyun    description:
90*4882a593Smuzhiyun      Debouncing periods in microseconds, one period per interrupt
91*4882a593Smuzhiyun      bank found in the controller
92*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/uint32-array
93*4882a593Smuzhiyun    minItems: 1
94*4882a593Smuzhiyun    maxItems: 5
95*4882a593Smuzhiyun
96*4882a593SmuzhiyunpatternProperties:
97*4882a593Smuzhiyun  # It's pretty scary, but the basic idea is that:
98*4882a593Smuzhiyun  #   - One node name can start with either s- or r- for PRCM nodes,
99*4882a593Smuzhiyun  #   - Then, the name itself can be any repetition of <string>- (to
100*4882a593Smuzhiyun  #     accomodate with nodes like uart4-rts-cts-pins), where each
101*4882a593Smuzhiyun  #     string can be either starting with 'p' but in a string longer
102*4882a593Smuzhiyun  #     than 3, or something that doesn't start with 'p',
103*4882a593Smuzhiyun  #   - Then, the bank name is optional and will be between pa and pg,
104*4882a593Smuzhiyun  #     pl or pm. Some pins groups that have several options will have
105*4882a593Smuzhiyun  #     the pin numbers then,
106*4882a593Smuzhiyun  #   - Finally, the name will end with either -pin or pins.
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun  "^([rs]-)?(([a-z0-9]{3,}|[a-oq-z][a-z0-9]*?)?-)+?(p[a-ilm][0-9]*?-)??pins?$":
109*4882a593Smuzhiyun    type: object
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun    properties:
112*4882a593Smuzhiyun      pins: true
113*4882a593Smuzhiyun      function: true
114*4882a593Smuzhiyun      bias-disable: true
115*4882a593Smuzhiyun      bias-pull-up: true
116*4882a593Smuzhiyun      bias-pull-down: true
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun      drive-strength:
119*4882a593Smuzhiyun        $ref: /schemas/types.yaml#/definitions/uint32
120*4882a593Smuzhiyun        enum: [10, 20, 30, 40]
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun    required:
123*4882a593Smuzhiyun      - pins
124*4882a593Smuzhiyun      - function
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun    additionalProperties: false
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun  "^vcc-p[a-hlm]-supply$":
129*4882a593Smuzhiyun    description:
130*4882a593Smuzhiyun      Power supplies for pin banks.
131*4882a593Smuzhiyun
132*4882a593Smuzhiyunrequired:
133*4882a593Smuzhiyun  - "#gpio-cells"
134*4882a593Smuzhiyun  - "#interrupt-cells"
135*4882a593Smuzhiyun  - compatible
136*4882a593Smuzhiyun  - reg
137*4882a593Smuzhiyun  - interrupts
138*4882a593Smuzhiyun  - clocks
139*4882a593Smuzhiyun  - clock-names
140*4882a593Smuzhiyun  - gpio-controller
141*4882a593Smuzhiyun  - interrupt-controller
142*4882a593Smuzhiyun
143*4882a593SmuzhiyunallOf:
144*4882a593Smuzhiyun  # FIXME: We should have the pin bank supplies here, but not a lot of
145*4882a593Smuzhiyun  # boards are defining it at the moment so it would generate a lot of
146*4882a593Smuzhiyun  # warnings.
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun  - if:
149*4882a593Smuzhiyun      properties:
150*4882a593Smuzhiyun        compatible:
151*4882a593Smuzhiyun          enum:
152*4882a593Smuzhiyun            - allwinner,sun50i-a100-pinctrl
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun    then:
155*4882a593Smuzhiyun      properties:
156*4882a593Smuzhiyun        interrupts:
157*4882a593Smuzhiyun          minItems: 7
158*4882a593Smuzhiyun          maxItems: 7
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun  - if:
161*4882a593Smuzhiyun      properties:
162*4882a593Smuzhiyun        compatible:
163*4882a593Smuzhiyun          enum:
164*4882a593Smuzhiyun            - allwinner,sun9i-a80-pinctrl
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun    then:
167*4882a593Smuzhiyun      properties:
168*4882a593Smuzhiyun        interrupts:
169*4882a593Smuzhiyun          minItems: 5
170*4882a593Smuzhiyun          maxItems: 5
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun  - if:
173*4882a593Smuzhiyun      properties:
174*4882a593Smuzhiyun        compatible:
175*4882a593Smuzhiyun          enum:
176*4882a593Smuzhiyun            - allwinner,sun6i-a31-pinctrl
177*4882a593Smuzhiyun            - allwinner,sun6i-a31s-pinctrl
178*4882a593Smuzhiyun            - allwinner,sun50i-h6-pinctrl
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun    then:
181*4882a593Smuzhiyun      properties:
182*4882a593Smuzhiyun        interrupts:
183*4882a593Smuzhiyun          minItems: 4
184*4882a593Smuzhiyun          maxItems: 4
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun  - if:
187*4882a593Smuzhiyun      properties:
188*4882a593Smuzhiyun        compatible:
189*4882a593Smuzhiyun          enum:
190*4882a593Smuzhiyun            - allwinner,sun8i-a23-pinctrl
191*4882a593Smuzhiyun            - allwinner,sun8i-a83t-pinctrl
192*4882a593Smuzhiyun            - allwinner,sun50i-a64-pinctrl
193*4882a593Smuzhiyun            - allwinner,sun50i-h5-pinctrl
194*4882a593Smuzhiyun            - allwinner,suniv-f1c100s-pinctrl
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun    then:
197*4882a593Smuzhiyun      properties:
198*4882a593Smuzhiyun        interrupts:
199*4882a593Smuzhiyun          minItems: 3
200*4882a593Smuzhiyun          maxItems: 3
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun  - if:
203*4882a593Smuzhiyun      properties:
204*4882a593Smuzhiyun        compatible:
205*4882a593Smuzhiyun          enum:
206*4882a593Smuzhiyun            - allwinner,sun6i-a31-r-pinctrl
207*4882a593Smuzhiyun            - allwinner,sun8i-a33-pinctrl
208*4882a593Smuzhiyun            - allwinner,sun8i-h3-pinctrl
209*4882a593Smuzhiyun            - allwinner,sun8i-v3-pinctrl
210*4882a593Smuzhiyun            - allwinner,sun8i-v3s-pinctrl
211*4882a593Smuzhiyun            - allwinner,sun9i-a80-r-pinctrl
212*4882a593Smuzhiyun            - allwinner,sun50i-h6-r-pinctrl
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun    then:
215*4882a593Smuzhiyun      properties:
216*4882a593Smuzhiyun        interrupts:
217*4882a593Smuzhiyun          minItems: 2
218*4882a593Smuzhiyun          maxItems: 2
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun  - if:
221*4882a593Smuzhiyun      properties:
222*4882a593Smuzhiyun        compatible:
223*4882a593Smuzhiyun          enum:
224*4882a593Smuzhiyun            - allwinner,sun4i-a10-pinctrl
225*4882a593Smuzhiyun            - allwinner,sun5i-a10s-pinctrl
226*4882a593Smuzhiyun            - allwinner,sun5i-a13-pinctrl
227*4882a593Smuzhiyun            - allwinner,sun7i-a20-pinctrl
228*4882a593Smuzhiyun            - allwinner,sun8i-a23-r-pinctrl
229*4882a593Smuzhiyun            - allwinner,sun8i-a83t-r-pinctrl
230*4882a593Smuzhiyun            - allwinner,sun8i-h3-r-pinctrl
231*4882a593Smuzhiyun            - allwinner,sun8i-r40-pinctrl
232*4882a593Smuzhiyun            - allwinner,sun50i-a64-r-pinctrl
233*4882a593Smuzhiyun            - allwinner,sun50i-a100-r-pinctrl
234*4882a593Smuzhiyun            - nextthing,gr8-pinctrl
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun    then:
237*4882a593Smuzhiyun      properties:
238*4882a593Smuzhiyun        interrupts:
239*4882a593Smuzhiyun          minItems: 1
240*4882a593Smuzhiyun          maxItems: 1
241*4882a593Smuzhiyun
242*4882a593SmuzhiyunadditionalProperties: false
243*4882a593Smuzhiyun
244*4882a593Smuzhiyunexamples:
245*4882a593Smuzhiyun  - |
246*4882a593Smuzhiyun    #include <dt-bindings/clock/sun5i-ccu.h>
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun    pio: pinctrl@1c20800 {
249*4882a593Smuzhiyun        compatible = "allwinner,sun5i-a13-pinctrl";
250*4882a593Smuzhiyun        reg = <0x01c20800 0x400>;
251*4882a593Smuzhiyun        interrupts = <28>;
252*4882a593Smuzhiyun        clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
253*4882a593Smuzhiyun        clock-names = "apb", "hosc", "losc";
254*4882a593Smuzhiyun        gpio-controller;
255*4882a593Smuzhiyun        interrupt-controller;
256*4882a593Smuzhiyun        #interrupt-cells = <3>;
257*4882a593Smuzhiyun        #gpio-cells = <3>;
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun        uart1_pe_pins: uart1-pe-pins {
260*4882a593Smuzhiyun            pins = "PE10", "PE11";
261*4882a593Smuzhiyun            function = "uart1";
262*4882a593Smuzhiyun        };
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun        uart1_pg_pins: uart1-pg-pins {
265*4882a593Smuzhiyun            pins = "PG3", "PG4";
266*4882a593Smuzhiyun            function = "uart1";
267*4882a593Smuzhiyun        };
268*4882a593Smuzhiyun    };
269