1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Xilinx ZynqMP Gigabit Transceiver PHY Device Tree Bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun This binding describes the Xilinx ZynqMP Gigabit Transceiver (GTR) PHY. The 14*4882a593Smuzhiyun GTR provides four lanes and is used by USB, SATA, PCIE, Display port and 15*4882a593Smuzhiyun Ethernet SGMII controllers. 16*4882a593Smuzhiyun 17*4882a593Smuzhiyunproperties: 18*4882a593Smuzhiyun "#phy-cells": 19*4882a593Smuzhiyun const: 4 20*4882a593Smuzhiyun description: | 21*4882a593Smuzhiyun The cells contain the following arguments. 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun - description: The GTR lane 24*4882a593Smuzhiyun minimum: 0 25*4882a593Smuzhiyun maximum: 3 26*4882a593Smuzhiyun - description: The PHY type 27*4882a593Smuzhiyun enum: 28*4882a593Smuzhiyun - PHY_TYPE_DP 29*4882a593Smuzhiyun - PHY_TYPE_PCIE 30*4882a593Smuzhiyun - PHY_TYPE_SATA 31*4882a593Smuzhiyun - PHY_TYPE_SGMII 32*4882a593Smuzhiyun - PHY_TYPE_USB 33*4882a593Smuzhiyun - description: The PHY instance 34*4882a593Smuzhiyun minimum: 0 35*4882a593Smuzhiyun maximum: 1 # for DP, SATA or USB 36*4882a593Smuzhiyun maximum: 3 # for PCIE or SGMII 37*4882a593Smuzhiyun - description: The reference clock number 38*4882a593Smuzhiyun minimum: 0 39*4882a593Smuzhiyun maximum: 3 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun compatible: 42*4882a593Smuzhiyun enum: 43*4882a593Smuzhiyun - xlnx,zynqmp-psgtr-v1.1 44*4882a593Smuzhiyun - xlnx,zynqmp-psgtr 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun clocks: 47*4882a593Smuzhiyun minItems: 1 48*4882a593Smuzhiyun maxItems: 4 49*4882a593Smuzhiyun description: | 50*4882a593Smuzhiyun Clock for each PS_MGTREFCLK[0-3] reference clock input. Unconnected 51*4882a593Smuzhiyun inputs shall not have an entry. 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun clock-names: 54*4882a593Smuzhiyun minItems: 1 55*4882a593Smuzhiyun maxItems: 4 56*4882a593Smuzhiyun items: 57*4882a593Smuzhiyun pattern: "^ref[0-3]$" 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun reg: 60*4882a593Smuzhiyun items: 61*4882a593Smuzhiyun - description: SERDES registers block 62*4882a593Smuzhiyun - description: SIOU registers block 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun reg-names: 65*4882a593Smuzhiyun items: 66*4882a593Smuzhiyun - const: serdes 67*4882a593Smuzhiyun - const: siou 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun xlnx,tx-termination-fix: 70*4882a593Smuzhiyun description: | 71*4882a593Smuzhiyun Include this for fixing functional issue with the TX termination 72*4882a593Smuzhiyun resistance in GT, which can be out of spec for the XCZU9EG silicon 73*4882a593Smuzhiyun version. 74*4882a593Smuzhiyun type: boolean 75*4882a593Smuzhiyun 76*4882a593Smuzhiyunrequired: 77*4882a593Smuzhiyun - "#phy-cells" 78*4882a593Smuzhiyun - compatible 79*4882a593Smuzhiyun - reg 80*4882a593Smuzhiyun - reg-names 81*4882a593Smuzhiyun 82*4882a593Smuzhiyunif: 83*4882a593Smuzhiyun properties: 84*4882a593Smuzhiyun compatible: 85*4882a593Smuzhiyun const: xlnx,zynqmp-psgtr-v1.1 86*4882a593Smuzhiyun 87*4882a593Smuzhiyunthen: 88*4882a593Smuzhiyun properties: 89*4882a593Smuzhiyun xlnx,tx-termination-fix: false 90*4882a593Smuzhiyun 91*4882a593SmuzhiyunadditionalProperties: false 92*4882a593Smuzhiyun 93*4882a593Smuzhiyunexamples: 94*4882a593Smuzhiyun - | 95*4882a593Smuzhiyun phy: phy@fd400000 { 96*4882a593Smuzhiyun compatible = "xlnx,zynqmp-psgtr-v1.1"; 97*4882a593Smuzhiyun reg = <0xfd400000 0x40000>, 98*4882a593Smuzhiyun <0xfd3d0000 0x1000>; 99*4882a593Smuzhiyun reg-names = "serdes", "siou"; 100*4882a593Smuzhiyun clocks = <&refclks 3>, <&refclks 2>, <&refclks 0>; 101*4882a593Smuzhiyun clock-names = "ref1", "ref2", "ref3"; 102*4882a593Smuzhiyun #phy-cells = <4>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun... 106