1*4882a593SmuzhiyunST SPEAr miphy DT details 2*4882a593Smuzhiyun========================= 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunST Microelectronics SPEAr miphy is a phy controller supporting PCIe and SATA. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible : should be "st,spear1310-miphy" or "st,spear1340-miphy" 8*4882a593Smuzhiyun- reg : offset and length of the PHY register set. 9*4882a593Smuzhiyun- misc: phandle for the syscon node to access misc registers 10*4882a593Smuzhiyun- #phy-cells : from the generic PHY bindings, must be 1. 11*4882a593Smuzhiyun - cell[1]: 0 if phy used for SATA, 1 for PCIe. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunOptional properties: 14*4882a593Smuzhiyun- phy-id: Instance id of the phy. Only required when there are multiple phys 15*4882a593Smuzhiyun present on a implementation. 16