1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3ss-phy.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Socionext UniPhier USB3 Super-Speed (SS) PHY 8*4882a593Smuzhiyun 9*4882a593Smuzhiyundescription: | 10*4882a593Smuzhiyun This describes the devicetree bindings for PHY interfaces built into 11*4882a593Smuzhiyun USB3 controller implemented on Socionext UniPhier SoCs. 12*4882a593Smuzhiyun Although the controller includes High-Speed PHY and Super-Speed PHY, 13*4882a593Smuzhiyun this describes about Super-Speed PHY. 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunmaintainers: 16*4882a593Smuzhiyun - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyunproperties: 19*4882a593Smuzhiyun compatible: 20*4882a593Smuzhiyun enum: 21*4882a593Smuzhiyun - socionext,uniphier-pro4-usb3-ssphy 22*4882a593Smuzhiyun - socionext,uniphier-pro5-usb3-ssphy 23*4882a593Smuzhiyun - socionext,uniphier-pxs2-usb3-ssphy 24*4882a593Smuzhiyun - socionext,uniphier-ld20-usb3-ssphy 25*4882a593Smuzhiyun - socionext,uniphier-pxs3-usb3-ssphy 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun reg: 28*4882a593Smuzhiyun description: PHY register region (offset and length) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun "#phy-cells": 31*4882a593Smuzhiyun const: 0 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun clocks: 34*4882a593Smuzhiyun minItems: 2 35*4882a593Smuzhiyun maxItems: 3 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun clock-names: 38*4882a593Smuzhiyun oneOf: 39*4882a593Smuzhiyun - items: # for Pro4, Pro5 40*4882a593Smuzhiyun - const: gio 41*4882a593Smuzhiyun - const: link 42*4882a593Smuzhiyun - items: # for PXs3 with phy-ext 43*4882a593Smuzhiyun - const: link 44*4882a593Smuzhiyun - const: phy 45*4882a593Smuzhiyun - const: phy-ext 46*4882a593Smuzhiyun - items: # for others 47*4882a593Smuzhiyun - const: link 48*4882a593Smuzhiyun - const: phy 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun resets: 51*4882a593Smuzhiyun maxItems: 2 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun reset-names: 54*4882a593Smuzhiyun oneOf: 55*4882a593Smuzhiyun - items: # for Pro4,Pro5 56*4882a593Smuzhiyun - const: gio 57*4882a593Smuzhiyun - const: link 58*4882a593Smuzhiyun - items: # for others 59*4882a593Smuzhiyun - const: link 60*4882a593Smuzhiyun - const: phy 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun vbus-supply: 63*4882a593Smuzhiyun description: A phandle to the regulator for USB VBUS 64*4882a593Smuzhiyun 65*4882a593Smuzhiyunrequired: 66*4882a593Smuzhiyun - compatible 67*4882a593Smuzhiyun - reg 68*4882a593Smuzhiyun - "#phy-cells" 69*4882a593Smuzhiyun - clocks 70*4882a593Smuzhiyun - clock-names 71*4882a593Smuzhiyun - resets 72*4882a593Smuzhiyun - reset-names 73*4882a593Smuzhiyun - vbus-supply 74*4882a593Smuzhiyun 75*4882a593SmuzhiyunadditionalProperties: false 76*4882a593Smuzhiyun 77*4882a593Smuzhiyunexamples: 78*4882a593Smuzhiyun - | 79*4882a593Smuzhiyun usb-glue@65b00000 { 80*4882a593Smuzhiyun compatible = "socionext,uniphier-ld20-dwc3-glue", 81*4882a593Smuzhiyun "simple-mfd"; 82*4882a593Smuzhiyun #address-cells = <1>; 83*4882a593Smuzhiyun #size-cells = <1>; 84*4882a593Smuzhiyun ranges = <0 0x65b00000 0x400>; 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun usb_ssphy0: ss-phy@300 { 87*4882a593Smuzhiyun compatible = "socionext,uniphier-ld20-usb3-ssphy"; 88*4882a593Smuzhiyun reg = <0x300 0x10>; 89*4882a593Smuzhiyun #phy-cells = <0>; 90*4882a593Smuzhiyun clock-names = "link", "phy"; 91*4882a593Smuzhiyun clocks = <&sys_clk 14>, <&sys_clk 16>; 92*4882a593Smuzhiyun reset-names = "link", "phy"; 93*4882a593Smuzhiyun resets = <&sys_rst 14>, <&sys_rst 16>; 94*4882a593Smuzhiyun vbus-supply = <&usb_vbus0>; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun }; 97