1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/phy/socionext,uniphier-usb2-phy.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Socionext UniPhier USB2 PHY 8*4882a593Smuzhiyun 9*4882a593Smuzhiyundescription: | 10*4882a593Smuzhiyun This describes the devicetree bindings for PHY interface built into 11*4882a593Smuzhiyun USB2 controller implemented on Socionext UniPhier SoCs. 12*4882a593Smuzhiyun Pro4 SoC has both USB2 and USB3 host controllers, however, this USB3 13*4882a593Smuzhiyun controller doesn't include its own High-Speed PHY. This needs to specify 14*4882a593Smuzhiyun USB2 PHY instead of USB3 HS-PHY. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunmaintainers: 17*4882a593Smuzhiyun - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyunproperties: 20*4882a593Smuzhiyun compatible: 21*4882a593Smuzhiyun enum: 22*4882a593Smuzhiyun - socionext,uniphier-pro4-usb2-phy 23*4882a593Smuzhiyun - socionext,uniphier-ld11-usb2-phy 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun "#address-cells": 26*4882a593Smuzhiyun const: 1 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun "#size-cells": 29*4882a593Smuzhiyun const: 0 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunpatternProperties: 32*4882a593Smuzhiyun "^phy@[0-9]+$": 33*4882a593Smuzhiyun type: object 34*4882a593Smuzhiyun additionalProperties: false 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun properties: 37*4882a593Smuzhiyun reg: 38*4882a593Smuzhiyun minimum: 0 39*4882a593Smuzhiyun maximum: 3 40*4882a593Smuzhiyun description: 41*4882a593Smuzhiyun The ID number for the PHY 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun "#phy-cells": 44*4882a593Smuzhiyun const: 0 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun required: 47*4882a593Smuzhiyun - reg 48*4882a593Smuzhiyun - "#phy-cells" 49*4882a593Smuzhiyun 50*4882a593Smuzhiyunrequired: 51*4882a593Smuzhiyun - compatible 52*4882a593Smuzhiyun - "#address-cells" 53*4882a593Smuzhiyun - "#size-cells" 54*4882a593Smuzhiyun 55*4882a593SmuzhiyunadditionalProperties: false 56*4882a593Smuzhiyun 57*4882a593Smuzhiyunexamples: 58*4882a593Smuzhiyun - | 59*4882a593Smuzhiyun // The UniPhier usb2-phy should be a subnode of a "syscon" compatible node. 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun soc-glue@5f800000 { 62*4882a593Smuzhiyun compatible = "socionext,uniphier-ld11-soc-glue", "simple-mfd", "syscon"; 63*4882a593Smuzhiyun reg = <0x5f800000 0x2000>; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun usb-controller { 66*4882a593Smuzhiyun compatible = "socionext,uniphier-ld11-usb2-phy"; 67*4882a593Smuzhiyun #address-cells = <1>; 68*4882a593Smuzhiyun #size-cells = <0>; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun usb_phy0: phy@0 { 71*4882a593Smuzhiyun reg = <0>; 72*4882a593Smuzhiyun #phy-cells = <0>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun usb_phy1: phy@1 { 76*4882a593Smuzhiyun reg = <1>; 77*4882a593Smuzhiyun #phy-cells = <0>; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun usb_phy2: phy@2 { 81*4882a593Smuzhiyun reg = <2>; 82*4882a593Smuzhiyun #phy-cells = <0>; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun }; 85*4882a593Smuzhiyun }; 86