xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/phy/socionext,uniphier-ahci-phy.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Socionext UniPhier AHCI PHY
8*4882a593Smuzhiyun
9*4882a593Smuzhiyundescription: |
10*4882a593Smuzhiyun  This describes the deivcetree bindings for PHY interfaces built into
11*4882a593Smuzhiyun  AHCI controller implemented on Socionext UniPhier SoCs.
12*4882a593Smuzhiyun
13*4882a593Smuzhiyunmaintainers:
14*4882a593Smuzhiyun  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyunproperties:
17*4882a593Smuzhiyun  compatible:
18*4882a593Smuzhiyun    enum:
19*4882a593Smuzhiyun      - socionext,uniphier-pxs2-ahci-phy
20*4882a593Smuzhiyun      - socionext,uniphier-pxs3-ahci-phy
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun  reg:
23*4882a593Smuzhiyun    description: PHY register region (offset and length)
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun  "#phy-cells":
26*4882a593Smuzhiyun    const: 0
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun  clocks:
29*4882a593Smuzhiyun    maxItems: 2
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun  clock-names:
32*4882a593Smuzhiyun    oneOf:
33*4882a593Smuzhiyun      - items:          # for PXs2
34*4882a593Smuzhiyun          - const: link
35*4882a593Smuzhiyun      - items:          # for others
36*4882a593Smuzhiyun          - const: link
37*4882a593Smuzhiyun          - const: phy
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun  resets:
40*4882a593Smuzhiyun    maxItems: 2
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun  reset-names:
43*4882a593Smuzhiyun    items:
44*4882a593Smuzhiyun      - const: link
45*4882a593Smuzhiyun      - const: phy
46*4882a593Smuzhiyun
47*4882a593Smuzhiyunrequired:
48*4882a593Smuzhiyun  - compatible
49*4882a593Smuzhiyun  - reg
50*4882a593Smuzhiyun  - "#phy-cells"
51*4882a593Smuzhiyun  - clocks
52*4882a593Smuzhiyun  - clock-names
53*4882a593Smuzhiyun  - resets
54*4882a593Smuzhiyun  - reset-names
55*4882a593Smuzhiyun
56*4882a593SmuzhiyunadditionalProperties: false
57*4882a593Smuzhiyun
58*4882a593Smuzhiyunexamples:
59*4882a593Smuzhiyun  - |
60*4882a593Smuzhiyun    ahci-glue@65700000 {
61*4882a593Smuzhiyun        compatible = "socionext,uniphier-pxs3-ahci-glue",
62*4882a593Smuzhiyun                     "simple-mfd";
63*4882a593Smuzhiyun        #address-cells = <1>;
64*4882a593Smuzhiyun        #size-cells = <1>;
65*4882a593Smuzhiyun        ranges = <0 0x65700000 0x100>;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun        ahci_phy: phy@10 {
68*4882a593Smuzhiyun            compatible = "socionext,uniphier-pxs3-ahci-phy";
69*4882a593Smuzhiyun            reg = <0x10 0x10>;
70*4882a593Smuzhiyun            #phy-cells = <0>;
71*4882a593Smuzhiyun            clock-names = "link", "phy";
72*4882a593Smuzhiyun            clocks = <&sys_clk 28>, <&sys_clk 30>;
73*4882a593Smuzhiyun            reset-names = "link", "phy";
74*4882a593Smuzhiyun            resets = <&sys_rst 28>, <&sys_rst 30>;
75*4882a593Smuzhiyun        };
76*4882a593Smuzhiyun    };
77