xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: Samsung SoC series UFS PHY Device Tree Bindings
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Alim Akhtar <alim.akhtar@samsung.com>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyunproperties:
13*4882a593Smuzhiyun  "#phy-cells":
14*4882a593Smuzhiyun    const: 0
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun  compatible:
17*4882a593Smuzhiyun    enum:
18*4882a593Smuzhiyun      - samsung,exynos7-ufs-phy
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun  reg:
21*4882a593Smuzhiyun    maxItems: 1
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun  reg-names:
24*4882a593Smuzhiyun    items:
25*4882a593Smuzhiyun      - const: phy-pma
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun  clocks:
28*4882a593Smuzhiyun    items:
29*4882a593Smuzhiyun      - description: PLL reference clock
30*4882a593Smuzhiyun      - description: symbol clock for input symbol ( rx0-ch0 symbol clock)
31*4882a593Smuzhiyun      - description: symbol clock for input symbol ( rx1-ch1 symbol clock)
32*4882a593Smuzhiyun      - description: symbol clock for output symbol ( tx0 symbol clock)
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun  clock-names:
35*4882a593Smuzhiyun    items:
36*4882a593Smuzhiyun      - const: ref_clk
37*4882a593Smuzhiyun      - const: rx1_symbol_clk
38*4882a593Smuzhiyun      - const: rx0_symbol_clk
39*4882a593Smuzhiyun      - const: tx0_symbol_clk
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun  samsung,pmu-syscon:
42*4882a593Smuzhiyun    $ref: '/schemas/types.yaml#/definitions/phandle'
43*4882a593Smuzhiyun    description: phandle for PMU system controller interface, used to
44*4882a593Smuzhiyun                 control pmu registers bits for ufs m-phy
45*4882a593Smuzhiyun
46*4882a593Smuzhiyunrequired:
47*4882a593Smuzhiyun  - "#phy-cells"
48*4882a593Smuzhiyun  - compatible
49*4882a593Smuzhiyun  - reg
50*4882a593Smuzhiyun  - reg-names
51*4882a593Smuzhiyun  - clocks
52*4882a593Smuzhiyun  - clock-names
53*4882a593Smuzhiyun  - samsung,pmu-syscon
54*4882a593Smuzhiyun
55*4882a593SmuzhiyunadditionalProperties: false
56*4882a593Smuzhiyun
57*4882a593Smuzhiyunexamples:
58*4882a593Smuzhiyun  - |
59*4882a593Smuzhiyun    #include <dt-bindings/clock/exynos7-clk.h>
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun    ufs_phy: ufs-phy@15571800 {
62*4882a593Smuzhiyun        compatible = "samsung,exynos7-ufs-phy";
63*4882a593Smuzhiyun        reg = <0x15571800 0x240>;
64*4882a593Smuzhiyun        reg-names = "phy-pma";
65*4882a593Smuzhiyun        samsung,pmu-syscon = <&pmu_system_controller>;
66*4882a593Smuzhiyun        #phy-cells = <0>;
67*4882a593Smuzhiyun        clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
68*4882a593Smuzhiyun                 <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
69*4882a593Smuzhiyun                 <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
70*4882a593Smuzhiyun                 <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
71*4882a593Smuzhiyun        clock-names = "ref_clk", "rx1_symbol_clk",
72*4882a593Smuzhiyun                      "rx0_symbol_clk", "tx0_symbol_clk";
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun    };
75*4882a593Smuzhiyun...
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