1*4882a593SmuzhiyunRockchip specific extensions to the Analogix Display Port PHY 2*4882a593Smuzhiyun------------------------------------ 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunRequired properties: 5*4882a593Smuzhiyun- compatible : should be one of the following supported values: 6*4882a593Smuzhiyun - "rockchip.rk3288-dp-phy" 7*4882a593Smuzhiyun- clocks: from common clock binding: handle to dp clock. 8*4882a593Smuzhiyun of memory mapped region. 9*4882a593Smuzhiyun- clock-names: from common clock binding: 10*4882a593Smuzhiyun Required elements: "24m" 11*4882a593Smuzhiyun- #phy-cells : from the generic PHY bindings, must be 0; 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunExample: 14*4882a593Smuzhiyun 15*4882a593Smuzhiyungrf: syscon@ff770000 { 16*4882a593Smuzhiyun compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun... 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun edp_phy: edp-phy { 21*4882a593Smuzhiyun compatible = "rockchip,rk3288-dp-phy"; 22*4882a593Smuzhiyun clocks = <&cru SCLK_EDP_24M>; 23*4882a593Smuzhiyun clock-names = "24m"; 24*4882a593Smuzhiyun #phy-cells = <0>; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun}; 27