1*4882a593Smuzhiyun* Renesas R-Car generation 2 USB PHY 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis file provides information on what the device node for the R-Car generation 4*4882a593Smuzhiyun2 USB PHY contains. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible: "renesas,usb-phy-r8a7742" if the device is a part of R8A7742 SoC. 8*4882a593Smuzhiyun "renesas,usb-phy-r8a7743" if the device is a part of R8A7743 SoC. 9*4882a593Smuzhiyun "renesas,usb-phy-r8a7744" if the device is a part of R8A7744 SoC. 10*4882a593Smuzhiyun "renesas,usb-phy-r8a7745" if the device is a part of R8A7745 SoC. 11*4882a593Smuzhiyun "renesas,usb-phy-r8a77470" if the device is a part of R8A77470 SoC. 12*4882a593Smuzhiyun "renesas,usb-phy-r8a7790" if the device is a part of R8A7790 SoC. 13*4882a593Smuzhiyun "renesas,usb-phy-r8a7791" if the device is a part of R8A7791 SoC. 14*4882a593Smuzhiyun "renesas,usb-phy-r8a7794" if the device is a part of R8A7794 SoC. 15*4882a593Smuzhiyun "renesas,rcar-gen2-usb-phy" for a generic R-Car Gen2 or 16*4882a593Smuzhiyun RZ/G1 compatible device. 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun When compatible with the generic version, nodes must list the 19*4882a593Smuzhiyun SoC-specific version corresponding to the platform first 20*4882a593Smuzhiyun followed by the generic version. 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun- reg: offset and length of the register block. 23*4882a593Smuzhiyun- #address-cells: number of address cells for the USB channel subnodes, must 24*4882a593Smuzhiyun be <1>. 25*4882a593Smuzhiyun- #size-cells: number of size cells for the USB channel subnodes, must be <0>. 26*4882a593Smuzhiyun- clocks: clock phandle and specifier pair. 27*4882a593Smuzhiyun- clock-names: string, clock input name, must be "usbhs". 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunThe USB PHY device tree node should have the subnodes corresponding to the USB 30*4882a593Smuzhiyunchannels. These subnodes must contain the following properties: 31*4882a593Smuzhiyun- reg: the USB controller selector; see the table below for the values. 32*4882a593Smuzhiyun- #phy-cells: see phy-bindings.txt in the same directory, must be <1>. 33*4882a593Smuzhiyun 34*4882a593SmuzhiyunThe phandle's argument in the PHY specifier is the USB controller selector for 35*4882a593Smuzhiyunthe USB channel other than r8a77470 SoC; see the selector meanings below: 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun+-----------+---------------+---------------+ 38*4882a593Smuzhiyun|\ Selector | | | 39*4882a593Smuzhiyun+ --------- + 0 | 1 | 40*4882a593Smuzhiyun| Channel \| | | 41*4882a593Smuzhiyun+-----------+---------------+---------------+ 42*4882a593Smuzhiyun| 0 | PCI EHCI/OHCI | HS-USB | 43*4882a593Smuzhiyun| 2 | PCI EHCI/OHCI | xHCI | 44*4882a593Smuzhiyun+-----------+---------------+---------------+ 45*4882a593Smuzhiyun 46*4882a593SmuzhiyunFor r8a77470 SoC;see the selector meaning below: 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun+-----------+---------------+---------------+ 49*4882a593Smuzhiyun|\ Selector | | | 50*4882a593Smuzhiyun+ --------- + 0 | 1 | 51*4882a593Smuzhiyun| Channel \| | | 52*4882a593Smuzhiyun+-----------+---------------+---------------+ 53*4882a593Smuzhiyun| 0 | EHCI/OHCI | HS-USB | 54*4882a593Smuzhiyun+-----------+---------------+---------------+ 55*4882a593Smuzhiyun 56*4882a593SmuzhiyunExample (Lager board): 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun usb-phy@e6590100 { 59*4882a593Smuzhiyun compatible = "renesas,usb-phy-r8a7790", "renesas,rcar-gen2-usb-phy"; 60*4882a593Smuzhiyun reg = <0 0xe6590100 0 0x100>; 61*4882a593Smuzhiyun #address-cells = <1>; 62*4882a593Smuzhiyun #size-cells = <0>; 63*4882a593Smuzhiyun clocks = <&cpg CPG_MOD 704>; 64*4882a593Smuzhiyun clock-names = "usbhs"; 65*4882a593Smuzhiyun power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; 66*4882a593Smuzhiyun resets = <&cpg 704>; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun usb0: usb-channel@0 { 69*4882a593Smuzhiyun reg = <0>; 70*4882a593Smuzhiyun #phy-cells = <1>; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun usb2: usb-channel@2 { 73*4882a593Smuzhiyun reg = <2>; 74*4882a593Smuzhiyun #phy-cells = <1>; 75*4882a593Smuzhiyun }; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593SmuzhiyunExample (iWave RZ/G1C sbc): 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun usbphy0: usb-phy0@e6590100 { 81*4882a593Smuzhiyun compatible = "renesas,usb-phy-r8a77470", 82*4882a593Smuzhiyun "renesas,rcar-gen2-usb-phy"; 83*4882a593Smuzhiyun reg = <0 0xe6590100 0 0x100>; 84*4882a593Smuzhiyun #address-cells = <1>; 85*4882a593Smuzhiyun #size-cells = <0>; 86*4882a593Smuzhiyun clocks = <&cpg CPG_MOD 704>; 87*4882a593Smuzhiyun clock-names = "usbhs"; 88*4882a593Smuzhiyun power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 89*4882a593Smuzhiyun resets = <&cpg 704>; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun usb0: usb-channel@0 { 92*4882a593Smuzhiyun reg = <0>; 93*4882a593Smuzhiyun #phy-cells = <1>; 94*4882a593Smuzhiyun }; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun usbphy1: usb-phy@e6598100 { 98*4882a593Smuzhiyun compatible = "renesas,usb-phy-r8a77470", 99*4882a593Smuzhiyun "renesas,rcar-gen2-usb-phy"; 100*4882a593Smuzhiyun reg = <0 0xe6598100 0 0x100>; 101*4882a593Smuzhiyun #address-cells = <1>; 102*4882a593Smuzhiyun #size-cells = <0>; 103*4882a593Smuzhiyun clocks = <&cpg CPG_MOD 706>; 104*4882a593Smuzhiyun clock-names = "usbhs"; 105*4882a593Smuzhiyun power-domains = <&sysc R8A77470_PD_ALWAYS_ON>; 106*4882a593Smuzhiyun resets = <&cpg 706>; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun usb1: usb-channel@0 { 109*4882a593Smuzhiyun reg = <0>; 110*4882a593Smuzhiyun #phy-cells = <1>; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun }; 113