1*4882a593SmuzhiyunQualcomm PCIe2 PHY controller 2*4882a593Smuzhiyun============================= 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm 5*4882a593Smuzhiyunplatforms. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun - compatible: compatible list, should be: 9*4882a593Smuzhiyun "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun - reg: offset and length of the PHY register set. 12*4882a593Smuzhiyun - #phy-cells: must be 0. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun - clocks: a clock-specifier pair for the "pipe" clock 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun - vdda-vp-supply: phandle to low voltage regulator 17*4882a593Smuzhiyun - vdda-vph-supply: phandle to high voltage regulator 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun - resets: reset-specifier pairs for the "phy" and "pipe" resets 20*4882a593Smuzhiyun - reset-names: list of resets, should contain: 21*4882a593Smuzhiyun "phy" and "pipe" 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun - clock-output-names: name of the outgoing clock signal from the PHY PLL 24*4882a593Smuzhiyun - #clock-cells: must be 0 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunExample: 27*4882a593Smuzhiyun phy@7786000 { 28*4882a593Smuzhiyun compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; 29*4882a593Smuzhiyun reg = <0x07786000 0xb8>; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 32*4882a593Smuzhiyun resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, 33*4882a593Smuzhiyun <&gcc GCC_PCIE_0_PIPE_ARES>; 34*4882a593Smuzhiyun reset-names = "phy", "pipe"; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun vdda-vp-supply = <&vreg_l3_1p05>; 37*4882a593Smuzhiyun vdda-vph-supply = <&vreg_l5_1p8>; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun clock-output-names = "pcie_0_pipe_clk"; 40*4882a593Smuzhiyun #clock-cells = <0>; 41*4882a593Smuzhiyun #phy-cells = <0>; 42*4882a593Smuzhiyun }; 43