1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: "http://devicetree.org/schemas/phy/qcom,usb-hs-28nm.yaml#" 5*4882a593Smuzhiyun$schema: "http://devicetree.org/meta-schemas/core.yaml#" 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Qualcomm Synopsys DesignWare Core 28nm High-Speed PHY 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Bryan O'Donoghue <bryan.odonoghue@linaro.org> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun Qualcomm Low-Speed, Full-Speed, Hi-Speed 28nm USB PHY 14*4882a593Smuzhiyun 15*4882a593Smuzhiyunproperties: 16*4882a593Smuzhiyun compatible: 17*4882a593Smuzhiyun enum: 18*4882a593Smuzhiyun - qcom,usb-hs-28nm-femtophy 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun reg: 21*4882a593Smuzhiyun maxItems: 1 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun "#phy-cells": 24*4882a593Smuzhiyun const: 0 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun clocks: 27*4882a593Smuzhiyun items: 28*4882a593Smuzhiyun - description: rpmcc ref clock 29*4882a593Smuzhiyun - description: PHY AHB clock 30*4882a593Smuzhiyun - description: Rentention clock 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun clock-names: 33*4882a593Smuzhiyun items: 34*4882a593Smuzhiyun - const: ref 35*4882a593Smuzhiyun - const: ahb 36*4882a593Smuzhiyun - const: sleep 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun resets: 39*4882a593Smuzhiyun items: 40*4882a593Smuzhiyun - description: PHY core reset 41*4882a593Smuzhiyun - description: POR reset 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun reset-names: 44*4882a593Smuzhiyun items: 45*4882a593Smuzhiyun - const: phy 46*4882a593Smuzhiyun - const: por 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun vdd-supply: 49*4882a593Smuzhiyun description: phandle to the regulator VDD supply node. 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun vdda1p8-supply: 52*4882a593Smuzhiyun description: phandle to the regulator 1.8V supply node. 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun vdda3p3-supply: 55*4882a593Smuzhiyun description: phandle to the regulator 3.3V supply node. 56*4882a593Smuzhiyun 57*4882a593Smuzhiyunrequired: 58*4882a593Smuzhiyun - compatible 59*4882a593Smuzhiyun - reg 60*4882a593Smuzhiyun - "#phy-cells" 61*4882a593Smuzhiyun - clocks 62*4882a593Smuzhiyun - clock-names 63*4882a593Smuzhiyun - resets 64*4882a593Smuzhiyun - reset-names 65*4882a593Smuzhiyun - vdd-supply 66*4882a593Smuzhiyun - vdda1p8-supply 67*4882a593Smuzhiyun - vdda3p3-supply 68*4882a593Smuzhiyun 69*4882a593SmuzhiyunadditionalProperties: false 70*4882a593Smuzhiyun 71*4882a593Smuzhiyunexamples: 72*4882a593Smuzhiyun - | 73*4882a593Smuzhiyun #include <dt-bindings/clock/qcom,gcc-qcs404.h> 74*4882a593Smuzhiyun #include <dt-bindings/clock/qcom,rpmcc.h> 75*4882a593Smuzhiyun usb2_phy_prim: phy@7a000 { 76*4882a593Smuzhiyun compatible = "qcom,usb-hs-28nm-femtophy"; 77*4882a593Smuzhiyun reg = <0x0007a000 0x200>; 78*4882a593Smuzhiyun #phy-cells = <0>; 79*4882a593Smuzhiyun clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 80*4882a593Smuzhiyun <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 81*4882a593Smuzhiyun <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 82*4882a593Smuzhiyun clock-names = "ref", "ahb", "sleep"; 83*4882a593Smuzhiyun resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, 84*4882a593Smuzhiyun <&gcc GCC_USB2A_PHY_BCR>; 85*4882a593Smuzhiyun reset-names = "phy", "por"; 86*4882a593Smuzhiyun vdd-supply = <&vreg_l4_1p2>; 87*4882a593Smuzhiyun vdda1p8-supply = <&vreg_l5_1p8>; 88*4882a593Smuzhiyun vdda3p3-supply = <&vreg_l12_3p3>; 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun... 91