xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593SmuzhiyunNVIDIA Tegra194 P2U binding
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunTegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
4*4882a593SmuzhiyunSpeed) each interfacing with 12 and 8 P2U instances respectively.
5*4882a593SmuzhiyunA P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE
6*4882a593Smuzhiyuninterface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe
7*4882a593Smuzhiyunlane.
8*4882a593Smuzhiyun
9*4882a593SmuzhiyunRequired properties:
10*4882a593Smuzhiyun- compatible: For Tegra19x, must contain "nvidia,tegra194-p2u".
11*4882a593Smuzhiyun- reg: Should be the physical address space and length of respective each P2U
12*4882a593Smuzhiyun       instance.
13*4882a593Smuzhiyun- reg-names: Must include the entry "ctl".
14*4882a593Smuzhiyun
15*4882a593SmuzhiyunRequired properties for PHY port node:
16*4882a593Smuzhiyun- #phy-cells: Defined by generic PHY bindings.  Must be 0.
17*4882a593Smuzhiyun
18*4882a593SmuzhiyunRefer to phy/phy-bindings.txt for the generic PHY binding properties.
19*4882a593Smuzhiyun
20*4882a593SmuzhiyunExample:
21*4882a593Smuzhiyun
22*4882a593Smuzhiyunp2u_hsio_0: phy@3e10000 {
23*4882a593Smuzhiyun	compatible = "nvidia,tegra194-p2u";
24*4882a593Smuzhiyun	reg = <0x03e10000 0x10000>;
25*4882a593Smuzhiyun	reg-names = "ctl";
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun	#phy-cells = <0>;
28*4882a593Smuzhiyun};
29