1ROCKCHIP USB2.0 PHY WITH NANENG IP BLOCK 2 3Required properties (phy (parent) node): 4 - compatible : should be one of the listed compatibles: 5 * "rockchip,rv1126-usb2phy" 6 - reg : the address offset of grf for usb-phy configuration. 7 - rockchip,grf : phandle to the syscon managing the "general register files" 8 - clocks : phandle + phy specifier pair, for the input clocks of phy. 9 - clock-names : input clocks name of phy. 10 - resets : phandle + reset specifier pairs. 11 - reset-names : reset names of phy. 12 - #clock-cells : should be 0. 13 - clock-output-names : specify the 480m output clock name. 14 15Optional properties: 16 - assigned-clocks : phandle of usb 480m clock. 17 - assigned-clock-parents : parent of usb 480m clock, select between 18 usb-phy output 480m and xin24m. 19 Refer to clk/clock-bindings.txt for generic clock 20 consumer properties. 21 - vbus-supply : regulator phandle for vbus power source. 22 - wakeup-source : enable bvalid irq and linestate wakeup when suspend. 23 only work when suspend wakeup-config is not work. 24 - vup-gpios : gpio phandle for pull-up resistor on DM. this property 25 is specially provided to RV1126/RV1109 in order to 26 increase the amplitude of chirpK and successfully 27 complete high speed handshake. 28 29Required nodes : a sub-node is required for each port the phy provides. 30 The sub-node name is used to identify host or otg port, 31 and shall be the following entries: 32 * "otg-port" : the name of otg port. 33 * "host-port" : the name of host port. 34 35Required properties (port (child) node): 36 - #phy-cells : must be 0. See ./phy-bindings.txt for details. 37 - interrupts : specify an interrupt for each entry in interrupt-names. 38 - interrupt-names : a list which should be one of the following cases: 39 Regular case: 40 * "otg-id" : for the otg id interrupt. 41 * "otg-bvalid" : for the otg vbus interrupt. 42 * "linestate" : for the host/otg linestate interrupt. 43 * "disconnect" : for the host/otg disconnect interrupt. 44 45Optional properties: 46 - phy-supply : phandle to a regulator that provides power to VBUS. 47 See ./phy-bindings.txt for details. 48 - rockchip,vbus-always-on: when set, indicates that the otg vbus 49 is always powered on. 50 51Example: 52 53u2phy1: usb2-phy@ff4c8000 { 54 compatible = "rockchip,rv1126-usb2phy"; 55 reg = <0xff4c8000 0x8000>; 56 rockchip,grf = <&grf>; 57 clocks = <&pmucru CLK_USBPHY_HOST_REF>, <&cru PCLK_USBPHY_HOST>; 58 clock-names = "phyclk", "pclk"; 59 assigned-clocks = <&cru USB480M>; 60 assigned-clock-parents = <&u2phy1>; 61 resets = <&cru SRST_USBPHYPOR_HOST>, <&cru SRST_USBPHY_HOST_P>; 62 reset-names = "u2phy", "u2phy-apb"; 63 #clock-cells = <0>; 64 clock-output-names = "usb480m_phy"; 65 status = "disabled"; 66 67 u2phy_host: host-port { 68 #phy-cells = <0>; 69 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 71 interrupt-names = "linestate", "disconnect"; 72 status = "disabled"; 73 }; 74}; 75