xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-edp.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593SmuzhiyunRockchip Naneng eDP Transmitter PHY
2*4882a593Smuzhiyun-----------------------
3*4882a593Smuzhiyun
4*4882a593SmuzhiyunRequired properties:
5*4882a593Smuzhiyun- compatible:	should be "rockchip,rk3568-edp-phy"
6*4882a593Smuzhiyun- reg:		register range for the PHY.
7*4882a593Smuzhiyun- clocks:	Must contain an entry in clock-names.
8*4882a593Smuzhiyun		See ../clocks/clock-bindings.txt for details.
9*4882a593Smuzhiyun- clock-names:	Must contain "refclk" and "pclk".
10*4882a593Smuzhiyun- resets:	Must contain an entry for each in reset-names.
11*4882a593Smuzhiyun		See ../reset/reset.txt for details.
12*4882a593Smuzhiyun- reset-names:	Must contain "apb".
13*4882a593Smuzhiyun- #phy-cells:	Must be 0
14*4882a593Smuzhiyun
15*4882a593SmuzhiyunExample:
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun	edp_phy: edp-phy@fdcb0000 {
18*4882a593Smuzhiyun		compatible = "rockchip,rk3568-edp-phy";
19*4882a593Smuzhiyun		reg = <0x0 0xfdcb0000 0x0 0x8000>;
20*4882a593Smuzhiyun		clocks = <&pmucru XIN_OSC0_EDPPHY_G>, <&cru PCLK_EDPPHY_GRF>;
21*4882a593Smuzhiyun		clock-names = "refclk", "pclk";
22*4882a593Smuzhiyun		resets = <&cru SRST_P_EDPPHY_GRF>;
23*4882a593Smuzhiyun		reset-names = "apb";
24*4882a593Smuzhiyun		#phy-cells = <0>;
25*4882a593Smuzhiyun		status = "disabled";
26*4882a593Smuzhiyun	};
27